Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated September 20, 2024, claims 1-16 are active in
this application.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Foreign Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)
(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements filed September 20, 2024 have been considered.
Claim Objections
In claim 4, the word “is” should be changed to –are--.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the phrase "...a third current line configured to carry a third level of a current corresponds to a sum..." is unclear. It does not clearly state how the sum is achieved.
Claims 2-7 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claims 8-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 8, the phrase "...a third current line configured to carry a third level of a current corresponds to a sum..." is unclear. It does not clearly state how the sum is achieved.
In claim 8, the claim uses the "or" ("first bit line or a second bit line") for both the first and second memory cells, but later implies they both contribute to a summing circuit involving "first current line" (from first BL) and "second current line" (from second BL). It is unclear if the cells output to either BL arbitrarily, or if the first cell outputs to the first BL and the second cell to the second BL. The phrase makes the routing of the signals ambiguous.
Claims 9-16 are rejected because they depend on the indefiniteness of the claims from which they depend.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-7 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-7 of U.S. Patent No. 12125524 [‘524]. Although the claims at issue are not identical, they are not patentably distinct from each other because of the following reason.
The subject matter claimed in the instant application is fully disclosed in the patent and is covered by the patent since the patent and the application are claiming common subject matter, as follows.
Present Application
Patent ‘524
1. An electronic device comprising: a first memory cell configured to output a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight; a second memory cell configured to output a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and a summing circuit configured to generate an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line, wherein the summing circuit further comprising: a first current line configured to carry a first level of a current from the first bit line; a second current line configured to carry a second level of a current from the second bit line; a third current line configured to carry a third level of a current corresponds to a sum of the first level of the current of the first current line and the second level of the current of the second current line; and a node connected with the first current line, the second current line, and the third current line, wherein a level of voltage of the node corresponds to the sum of the level of the voltage received through the first bit line and the level of the voltage of the second bit line.
1. An electronic device comprising: a first memory cell configured to output only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight; a second memory cell configured to output only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and a summing circuit configured to generate an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line, wherein the summing circuit further comprising: a first transmission gate configured to transmit a level of a voltage received through the first bit line to a node; and a second transmission gate configured to transmit a level of a voltage received through the second bit line to the node; wherein a level of voltage of the node corresponds to a sum of the level of the voltage received through the first bit line and the level of the voltage of the second bit line, wherein the summing circuit further comprises a resistor connected to the node and a supply terminal of an operating voltage, and wherein a level of a current through the resistor corresponds to a sum of a level of a current through the first transmission gate and a level of a current through the second transmission gate.
2. The electronic device of claim 1, wherein, when data of a first logical value are received through the first word line and data of a second logical value are received through the second word line, the first input data of the first logical value are received by the first memory cell, and wherein, when data of the second logical value are received through the first word line and data of the first logical value are received through the second word line, the first input data of the second logical value are received by the first memory cell.
2. The electronic device of claim 1, wherein, when data of a first logical value are received through the first word line and data of a second logical value are received through the second word line, the first input data represents the first logical value, and wherein, when data of the second logical value are received through the first word line and data of the first logical value are received through the second word line, the first input data represents the second logical value.
3. The electronic device of claim 1, wherein the summing circuit is further configured to: generate the output voltage in response to a read signal.
3. The electronic device of claim 1, wherein the summing circuit is further configured to generate the output voltage in response to a read signal.
4. The electronic device of claim 1, wherein the first memory cell and the second memory cell is included in one column.
4. The electronic device of claim 1, wherein the first memory cell and the second memory cell are included in one column.
5. The electronic device of claim 1, further comprising a sense amplifier circuit configured to: amplify the output voltage based on a result of comparing the level of the output voltage and a level of a reference voltage.
5. The electronic device of claim 1, further comprising a sense amplifier circuit configured to amplify the output voltage based on a result of comparing the level of the output voltage and a level of a reference voltage.
6. The electronic device of claim 5, wherein the sense amplifier circuit is further configured to: increase the level of the output voltage when the level of the output voltage is greater than the level of the reference voltage; and decrease the level of the output voltage when the level of the output voltage is smaller than the level of the reference voltage.
6. The electronic device of claim 5, wherein the sense amplifier circuit is further configured to: increase the level of the output voltage when the level of the output voltage is greater than the level of the reference voltage; and decrease the level of the output voltage when the level of the output voltage is smaller than the level of the reference voltage.
7. The electronic device of claim 1, wherein the first memory cell is further configured to: store the first weight through a training operation performed according to a binary neural network algorithm.
7. The electronic device of claim 1, wherein the first memory cell is further configured to store the first weight during a training operation performed by a binary neural network algorithm.
As can be seen from the above table, similar to claim 1 of the present application, claim 1 of patent ‘524 recites “An electronic device comprising: a first memory cell configured to output…a first voltage through a first bit line…a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight; a second memory cell configured to output…a third voltage through the first bit line…a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and a summing circuit configured to generate an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line…” Unlike the application the patent recites “…the summing circuit further comprising: a first transmission gate configured to transmit a level of a voltage received through the first bit line to a node; and a second transmission gate configured to transmit a level of a voltage received through the second bit line to the node; wherein a level of voltage of the node corresponds to a sum of the level of the voltage received through the first bit line and the level of the voltage of the second bit line, wherein the summing circuit further comprises a resistor connected to the node and a supply terminal of an operating voltage, and wherein a level of a current through the resistor corresponds to a sum of a level of a current through the first transmission gate and a level of a current through the second transmission gate.”; whereas, the application recites “the summing circuit further comprising: a first current line configured to carry a first level of a current from the first bit line; a second current line configured to carry a second level of a current from the second bit line; a third current line configured to carry a third level of a current corresponds to a sum of the first level of the current of the first current line and the second level of the current of the second current line; and a node connected with the first current line, the second current line, and the third current line, wherein a level of voltage of the node corresponds to the sum of the level of the voltage received through the first bit line and the level of the voltage of the second bit line.” However, they conceptually match for the following reasons:
Both describe a summing node: Both circuits use a common node to combine currents from two inputs to create an output voltage.
Transmission Gate = Switch/Current Path: a transmission gate is a CMOS switch. The patent uses a transistor-based switch, while the application applies "current lines". A transmission gate passing voltage from a bit line directly creates a current that is summed at the node.
Resistor = Current to Voltage Converter: the patent specifically mentions a resistor, which is the standard way to convert the summed current (mentioned in both) into a summed voltage. The application assumes this relationship by saying "current... corresponds to a sum" and "voltage... corresponds to the sum".
Functionality: Both are describing a current-summing, voltage-output converter, which is commonly used in DACs or analog adder circuits.
Therefore, the patent protections have been granted to the earlier filed patent application.
With respect to claim 2, claim 2 of the application and claim 2 of the patent are similar in that both describe a system that maps two distinct input combinations to two distinct outcomes. Both indicating that the output value of a memory operation matches the data corresponding to the input conditions. Both describe the same input-to-output function of a circuit.
For similar reasons, claims 3-7 are rejected over claims 1-7 of patent ‘524.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 8 and 13 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. [US Patent Application # 20210263672].
With respect to claim 8, Chang et al. disclose an electronic device comprising: a first column including: a first memory cell configured to output first result data of a logical value determined according to a logical operation through a first bit line or a second bit line [“The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.” – pars. 0019-0020 and 0028 (describes a memory array with columns of cells (e.g., [0028]) configured to performing Multiply-Accumulate (MAC) operations, which are logical/arithmetic operations, outputting results onto read bitlines (RBLs).)], based on first input data input through a first word line and a first weight [“The storage element 122 is connected to the WWL associated with its row and WBL of its column, and is adapted to input the binary signal indicative a weight (“W”) (0 or 1) when activated by a signal on the WWL and store the weight.” – pars. 0021-0022 (The patent describes storing weights in memory cells ("store the weight value") and applying input data via wordlines to generate product signals (result data).)]; and a second memory cell configured to output second result data of a logical value determined according to the logical operation through the first bit line or the second bit line, based on second input data input through a second word line and a second weight [ Similar to the first cell, multiple cells in a column are activated to generate multiple product signals.]; and a summing circuit configured to output a sum of the first result data and the second result data [“ the sum of IN×W of all memory units 120 in the column 114 is obtained on the RBL.” – par. 0028 (The RBLs (read bitlines) act as a summation node for the current from multiple memory cells)], wherein the summing circuit further comprising: a first current line configured to carry a first level of a current from the first bit line [The RBLs carry currents corresponding to the product of weight and input. – pars. 0021-0022 and 0028]; a second current line configured to carry a second level of a current from the second bit line [Similar to above; RBLs sum currents from different cells. See pars. 0021-0022 and 0028]; a third current line configured to carry a third level of a current corresponds to a sum of the first level of the current of the first current line and the second level of the current of the second current line [“ the sum of IN×W of all memory units 120 in the column 114 is obtained on the RBL.” – par. 0028]; and a node connected with the first current line, the second current line, and the third current line [The read bitline (RBL) acts as the node where the currents are summed. – par. 0021-0022 and 0028], wherein a level of voltage of the node corresponds to the sum of the first result data and the second result data [“V.sub.RBL represents the sum of IN×W in all memory units 120 sharing the same RBL.” – pars. 0030 and 0035 (The RBL is the node where charge is summed, and V.sub.RBL is a voltage representation of the sum.)].
With respect to claim 13, Chang et al. disclose the first column further includes: memory cells storing data of a first logical value and memory cells storing data of a second logical value [“the weight values stored in storage elements 122 are 0 for the nth row and 1 for (n-1)th row” – par. 0027].
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 March 11, 2026