Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/30/2025, 10,08/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-6 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 11-15 of prior U.S. Patent No. US 11,144,385. This is a statutory double patenting rejection.
Claims 1-6 of instant application recites identical limitations of claims 11-15 of US 11,144,385.
Instant Application
US 11,144,385
As per claim 1:
A method, comprising:
receiving, by a memory device from a controller over a plurality of data lines, data to be written to an array of memory cells of the memory device;
determining, by the memory device, a timing offset for transmitting a checksum for the data; and
transmitting, from the memory device to the controller, the checksum at a transmit time that is shifted according to the timing offset.
As per claim 11:
A method, comprising:
receiving, by a memory device from a controller over a plurality of data lines, data to be written to an array of memory cells of the memory device;
determining, by the memory device, a timing offset for transmitting a checksum for the data; and
transmitting, from the memory device to the controller, the checksum at a transmit time that is shifted according to the timing offset.
As per claim 2:
selecting the timing offset from one or more preconfigured timing offsets,
wherein each preconfigured timing offset is based at least in part on an operating condition at the memory device.
As per claim 12:
selecting the timing offset from one or more preconfigured timing offsets,
wherein each preconfigured timing offset is based at least in part on an operating condition at the memory device.
As per claim 3:
receiving, during an initialization sequence, configuration information setting the one or more preconfigured timing offsets,
wherein selecting the timing offset from the one or more preconfigured timing offsets is based at least in part on the configuration information.
As per claim 13:
receiving, during an initialization sequence, configuration information setting the one or more preconfigured timing offsets,
wherein selecting the timing offset from the one or more preconfigured timing offsets is based at least in part on the configuration information.
As per claim 4:
storing the one or more preconfigured timing offsets in a first mode register …
As per claim 14:
storing the one or more preconfigured timing offsets in a mode register …
As per claim 6:
wherein the operating condition comprises a data termination state, or a driver strength, or both.
As per claim 15:
wherein the operating condition comprises a data termination state, or a driver strength, or both.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 7-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,144,385. Although the claims at issue are not identical, they are not patentably distinct from each other because
Instant Application
US 11,144,385
As per claim 7:
A method, comprising:
receiving, by a memory device from a controller over a plurality of data lines, data to be written to an array of memory cells of the memory device as part of a write operation;
receiving, by the memory device over
a first
line coupled with the controller during the write operation,
checksum information for the data received over the plurality of data lines;
detecting, by the memory device, an error in the data based at least in part on the checksum information and the write operation; and
transmitting, from the memory device to the controller, transmission failure information for the write operation indicating the error in the data based at least in part on detecting the error,
wherein the transmission failure information for the write operation is transmitted over a second line coupled with the memory device and the controller, the second line being different than the … line.
As per claim 1:
A method, comprising:
receiving, by a memory device from a controller over a plurality of data lines, data to be written to an array of memory cells of the memory device as part of a write operation;
receiving, by the memory device over
an error detection code (EDC)
line coupled with the controller during the write operation,
checksum information for the data received over the plurality of data lines;
detecting, by the memory device, an error in the data based at least in part on the checksum information and the write operation; and
transmitting, from the memory device to the controller, transmission failure information for the write operation indicating the error in the data based at least in part on detecting the error,
wherein the transmission failure information for the write operation is transmitted over a first line coupled with the memory device and the controller, the first line being different than the … line.
As per claim 17:
…
receive, from one or more controllers over a plurality of data lines, data to be written to the one or more memory arrays;
determine a timing offset for transmitting a checksum for the data, wherein the timing offset is programmed via multiple mode registers; and
transmit, to the one or more controllers, the checksum at a transmit time that is shifted according to the timing offset.
As per claim 11:
…
receiving, by a memory device from a controller over a plurality of data lines, data to be written to an array of memory cells of the memory device;
determining, by the memory device, a timing offset for transmitting a checksum for the data; and
transmitting, from the memory device to the controller, the checksum at a transmit time that is shifted according to the timing offset.
One of ordinary skill in the art would clearly recognize independent claims of current application is an obvious variation of the claimed subject matter of independent claims of patent US 11,144,385 because both recite a similar limitation of adjusting offset time (see claim 17 of instant application and claim 11 of US 11,144,385) and/ or of transmitting on different lines after detecting errors and perform checksum (see claim 7 of instant application and claim 1 of US 11,144,385). The differences are one application recites the “first line” instead of “EDC line”.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,709,730. Although the claims at issue are not identical, they are not patentably distinct from each other because
Instant Application
US 11,709,730
As per claim 7:
…
receiving, by a memory device from a controller over a plurality of data lines,
data to be written to an array of memory cells of the memory device as part of a write operation; receiving, by the memory device over a first line coupled with the controller during the write operation, checksum information for the data received over the plurality of data lines;
detecting, by the memory device, an error in the data based at least in part on the checksum information and the write operation; and
transmitting, from the memory device to the controller, transmission failure information for the write operation indicating the error in the data based at least in part on detecting the error,
wherein the transmission failure information for the write operation is transmitted over a second line coupled with the memory device and the controller, the second line being different than the … line.
As per claim 1:
…
receive, over a plurality of data lines, data to be written to the array of memory cells;
receive, over an error detection code (EDC) line and concurrent with receiving the data, a first signal comprising information for
detecting errors in the data, the EDC line being coupled with the memory device and the controller; and
transmit, to the controller over a first line that is different than the EDC line, a second signal indicating an error in the data that is detected using the information.
One of ordinary skill in the art would clearly recognize independent claims of current application is an obvious variation of the claimed subject matter of independent claims of patent US 11,709,730 because both recite a similar limitation of transmitting on different lines after detecting errors and perform checksum. The differences are one application recites the “first line” instead of “EDC line”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7-10, 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2013/0,179,760)
As per claim 7:
Lee discloses:
A method, comprising:
receiving, by a memory device from a controller over a plurality of data lines, data to be written to an array of memory cells of the memory device as part of a write operation;
(Lee, Fig. 3 shows the memory device 10 with data input buffer 100)
(Lee, Fig. 3 shows data input buffer 100 to receive parallel data and parallel CRC)
(Lee, [0051] The data input buffer 100 buffers a data transmitted from a host (not shown) through a plurality of data input pads DQ0 through DQk (k is a natural number). The data parallel circuit 200 converts a serial data and a serial CRC code output from the data input buffer 100 into a parallel data ADATA and a parallel CRC code ACRC, respectively).
receiving, by the memory device over a first line coupled with the controller during the write operation, checksum information for the data received over the plurality of data lines;
(Lee, Fig. 3 shows the memory device 10 with data input buffer 100)
(Lee, Fig. 3 shows data input buffer 100 to receive parallel data and parallel CRC)
(Lee, [0051] The data input buffer 100 buffers a data transmitted from a host (not shown) through a plurality of data input pads DQ0 through DQk (k is a natural number). The data parallel circuit 200 converts a serial data and a serial CRC code output from the data input buffer 100 into a parallel data ADATA and a parallel CRC code ACRC, respectively)
detecting, by the memory device, an error in the data based at least in part on the checksum information and the write operation; and
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
transmitting, from the memory device to the controller, transmission failure information for the write operation indicating the error in the data based at least in part on detecting the error,
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
wherein the transmission failure information for the write operation is transmitted over a second line coupled with the memory device and the controller,
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
the second line being different than the first line.
(Lee, Fig. 3 shows that the memory device 10 to receive data from data lines DQ0-DQK and the memory device 10 to output ERR return to HOST on different line from DQ0-DQK)
As per claim 8:
Lee further discloses:
generating a checksum for the data received over each data line of the plurality of data lines; and
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
comparing the generated checksum for the received data and the received checksum information, wherein detecting the error is based at least in part on comparing the generated checksum for the received data and the received checksum information.
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
As per claim 9:
Lee further discloses:
determining a difference between the generated checksum and the received checksum information based at least in part on comparing the generated checksum and the received checksum information, wherein detecting the error in the received data is based at least in part on the determined difference between the generated checksum and the received checksum information.
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
As per claim 10:
Lee further discloses:
refraining from transmitting a signal to the controller using the first line based at least in part on the transmission failure information transmitted over the second line.
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
As per claim 15:
Lee further discloses:
receiving, from the controller, a retransmission of the data to be written to the array of memory cells based at least in part on the transmission failure information indicating the error.
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
As per claim 16:
Lee further discloses:
transmitting a logic value that indicates the detected error in the received data.
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2013/0,179,760), in view of Nygren et al. (US 2013/0,290,767)
As per claim 11:
Lee does not clearly disclose:
transmitting a clock signal over a third line coupled with the controller, the third line being different than the first line, wherein the clock signal has a first frequency that is lower than a second frequency of the received data.
Nygren discloses:
transmitting a clock signal over a third line coupled with the controller, the third line being different than the first line, wherein the clock signal has a first frequency that is lower than a second frequency of the received data.
(Nygren [0022] FIG. 1 is an illustration of an example computer system 100 with a processing unit and a memory device. Computer system 100 includes a processing unit 110, a memory device 120, a data bus 130.sub.7-130.sub.0, an address/control (A/C) bus 140.sub.15-140.sub.0, and a clock signal 150 (e.g., a write clock signal))
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate a well-known method of transmitting/receiving a clock signal on different line than the data/checksum line because the clock signal cannot never use the same line as data/checksum/address signal.
(Nygren [0022] FIG. 1 is an illustration of an example computer system 100 with a processing unit and a memory device. Computer system 100 includes a processing unit 110, a memory device 120, a data bus 130.sub.7-130.sub.0, an address/control (A/C) bus 140.sub.15-140.sub.0, and a clock signal 150 (e.g., a write clock signal))
As per claim 12:
Nygren further discloses:
wherein the clock signal comprises a low-swing differential signal, or a hold pattern, or both.
(Nygren [0022] FIG. 1 is an illustration of an example computer system 100 with a processing unit and a memory device. Computer system 100 includes a processing unit 110, a memory device 120, a data bus 130.sub.7-130.sub.0, an address/control (A/C) bus 140.sub.15-140.sub.0, and a clock signal 150 (e.g., a write clock signal))
As per claim 13:
Lee further discloses:
wherein the transmission failure information is transmitted using a
(Lee, [0052] The CRC circuit 300 calculates a CRC code by using the parallel data ADATA output from the data parallel circuit 200. Also, the CRC circuit 300 compares the parallel CRC code ACRC output from the data parallel circuit 200 and the calculated CRC code with each other and detects an error of the serial data based on the result of comparison. The error of the serial data may denote an error that may have occurred in the process of the serial data transmission from a host through a channel)
Nygren further discloses:
transmitting a clock signal over the second line coupled with the controller, wherein the clock signal is transmitted
(Nygren [0022] FIG. 1 is an illustration of an example computer system 100 with a processing unit and a memory device. Computer system 100 includes a processing unit 110, a memory device 120, a data bus 130.sub.7-130.sub.0, an address/control (A/C) bus 140.sub.15-140.sub.0, and a clock signal 150 (e.g., a write clock signal))
Lee-Nygren does not clearly mention first modulation scheme and/or second modulation scheme.
However, it would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to recognize that failure information (of LEE) transmit from memory device to controller does not have the same scheme as the clock signal (of Nygren) transmit from memory controller to memory device. The failure information and clock signal are transmitting and receiving in opposite/different direction. Therefore, the two signals are having different modulation scheme.
As per claim 14:
Nygren further discloses:
wherein the clock signal comprises a hold pattern.
(Nygren [0022] FIG. 1 is an illustration of an example computer system 100 with a processing unit and a memory device. Computer system 100 includes a processing unit 110, a memory device 120, a data bus 130.sub.7-130.sub.0, an address/control (A/C) bus 140.sub.15-140.sub.0, and a clock signal 150 (e.g., a write clock signal))
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Inoue et al. (US 2014/0,032,786) in figure 2 shows a host controller 1 to transmit data and command to memory device 10. Figure 5 shows the memory card with bridge circuit to receive data and command from host controller via 12d and 12C. The memory device to perform error check portion to generate CRC data based on the input data and input command. Response Reply portion 43 to response CRC data back to the host controller in a time period to satisfy response requirement.
(Inoue [0061] However, a reply time period for a CRC response is defined in the SD standards, and it is conceivable that a CRC response requirement may not be satisfied in a case where CRC responses from the SDIO controller 21a and the SD memory controller 22a are sent to the SD host controller 1a)
(Inoue [0063] ….the response reply portion 43 is configured on that, in a case where information regarding the command class from the command analysis portion 14 indicates it is necessary to return a CRC response in a short time period to satisfy a CRC response requirement, upon receiving an error check result from the error check portion 42, the response reply portion 43 sends the error check result received from the error check portion 42 to the SD host controller 1a as the CRC response)
Zerbe et al. (US 2013/0,254,585) discloses a method of communicating with the first memory device in accordance with the first timing and… determining timing adjustments based on feedback from the first memory device and modifying the first timing based on the timing adjustments. … with the second timing as modified by the timing adjustments and, while communicating with the second memory device, determining additional timing adjustments based on feedback from the second memory device and modifying the second timing based on the additional timing adjustments.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111