DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/26/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10 and 13 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by
Yamanda (JP H06276037A).
Regarding claim 1, Yamanda discloses a voltage buffer [see figs. 1-2], comprising: an output circuit [20] operable in a first voltage domain [+/-V1] and comprising an output node [OUT node], wherein the output circuit is controllable to provide an output voltage [OUT] at the output node; an input circuit [10] operable in a second voltage domain [+/-V2] and configured to receive an input voltage [IN] reference and a feedback signal [output signal from 30], wherein the input circuit is configured to generate an error signal [output signal 10/signal at node A] based on that corresponds to a difference between the feedback signal [output signal from 30] and the input voltage reference, and wherein the first voltage domain is a higher voltage than the second voltage domain [the power supply voltage + V2,-V2 of the voltage amplification stage 10 can be set to a voltage sufficiently lower than the power supply voltage + V1,-V1 of the power amplification stage 20, page 4]; a feedback circuit [30] coupled with the output circuit and the input circuit, wherein the feedback circuit [30] is configured to generate the feedback signal based on the output voltage [OUT]; a buffer bias circuit [60 including Q3 and Q4] coupled with the input circuit [10], wherein the buffer bias circuit is configured to provide a bias signal [signal at node B] and wherein the error signal adjusts the bias signal provided by the buffer bias circuit; and a level shifting circuit [40, 50] operable in the first voltage domain and coupled with the buffer bias circuit [60] and the output circuit [20], wherein the buffer bias circuit is coupled between the input circuit and the level shifting circuit [the buffer bias circuit 60 includes 50 (Q3 and Q4) provides the DC bias and operating conditions that allow level shifting circuit 40 to level shift the output of input circuit 10, therefore, the buffer bias is functionally between the input circuit and level shifting], wherein the level shifting circuit is configured to translate the adjusted bias signal from the second voltage domain [+/-V2] to the first voltage domain [+/-V1], and wherein the output circuit is controllable by the translated adjusted bias signal.
Regarding claim 9, Yamanda discloses a voltage buffer [see figs. 1-2], comprising: a feedback circuit [30]; an error amplifier [10] comprising a first input [(+)], a second input [(-)], and an error output [output of 10], wherein the first input is coupled with a voltage reference [IN], the second input is coupled with the feedback circuit, the error output corresponds to a difference between the second input and the first input, and wherein the error amplifier is further coupled to a second voltage supply [+/-V2]; an output circuit [20] comprising a sourcing transistor [Q5] coupled in series with a sinking transistor [Q6] and a first voltage supply [+/-V1], wherein: the sourcing transistor and sinking transistor are coupled at a first output node [OUT node]; the first output node is coupled with the feedback circuit [30]; and a first voltage [+V1] provided by the first voltage supply is greater than a second voltage [+V2] provided by the second voltage supply [the power supply voltage + V2,-V2 of the voltage amplification stage 10 can be set to a voltage sufficiently lower than the power supply voltage + V1,-V1 of the power amplification stage 20, ]; a level shifting circuit [40, 50] comprising a third input [node B] and a second output, wherein: the level shifting circuit is coupled with the first voltage supply; the second output is coupled with the sourcing transistor; and the level shifting circuit is configured to receive a voltage signal [output signal 10 at node A] on the third input, increase a voltage level of the received voltage signal [Va], and provide the increased voltage signal on the second output [node B]; and a buffer bias circuit [60] coupled with the error output and the third input, wherein the buffer bias circuit is coupled between the error amplifier and the level shifting circuit [the buffer bias circuit 60 includes 50 (Q3 and Q4) provides the DC bias and operating conditions that allow level shifting circuit 40 to level shift the output of error amplifier 10, therefore, the buffer bias is functionally between the error amplifier and level shifting circuit], wherein the buffer bias circuit is configured to control an operating point of the sourcing transistor [Q5] and an operating point of the sinking transistor [Q6].
Regarding claim 13, Yamanda discloses wherein the feedback circuit [30] is configured to: receive an output voltage [OUT] from the first output node; reduce a voltage level of the received output voltage; and provide the reduced output voltage to the second input of the error amplifier.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-5 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Yamanda in view of Tsuchi (US 2011/0298777) further in view of Bogner et al. (US 2018/0145673 and Bogner hereinafter).
Regarding claims 2 and 10, Yamanda discloses all the features with respect to claims 1 and 9 as outlined above. Yamanda further discloses wherein: each of the output circuit, buffer bias circuit, and level shifting circuit comprise one or more transistors [transistors in 40, 50 and 20]; the second voltage domain comprises a second operating voltage [operating voltage of +V2] less than or equal to a rated operational voltage limit of the one or more transistors [inherent: 10/40 uses transistors rated for vdd1 and intermediate voltage]. Yamanda does not explicitly disclose the input circuit comprise one or more transistors and the first voltage domain comprises a first operating voltage greater than the rated operational voltage limit of the one or more transistors, wherein the rated operational voltage limit is a foundry-recommended voltage limit.
However, Tsuchi discloses an amplifier [fig. 1] comprise one or more transistors. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Yamanda by incorporating transistor as taught in Tsuchi in order to provide known amplifier comprises made of transistors. Yamanda in view of Tsuchi does not explicitly disclose the first voltage domain comprises a first operating voltage greater than the rated operational voltage limit of the one or more transistors, wherein the rated operational voltage limit is a foundry-recommended voltage limit.
However, Bogner discloses a switching circuit maximum voltage level of the input voltage is higher than the applicable operational voltage [abstract, par. [0006]]. It would have been obvious to one of ordinary skill in the art before the effective filing date to select a voltage greater than the rated operational voltage limit for the desire performance and manufacturing specified voltage limit as taught in Bonert the use of manufacturing specified voltage limit would have been an obvious design choice or routine parameter selection.
Regarding claims 3-5 and 11-12, Yamanda in view of Tsuchi discloses all the features with respect to claims 2 and 10 as outlined above. Yamanda in view of Tsuchi does not explicitly disclose wherein the first operating voltage is about 5.0 Volts and the second operating voltage is about 2.8 Volts; wherein the input voltage reference is about 2.0 Volts and the output voltage is about 4.0 Volts; wherein the input voltage reference is about 2.0 Volts and the output voltage is about 4.0 Volts. Although Yamanda in view of Tsuchi does not discloses a voltage value, it would have been motivated to select operational voltages appropriate for the desire performance and to apply such a range, absent any criticality (i.e. unobvious and/or unexpected result(s)), is generally achievable through routine optimization/experimentation, and since discovering the optimum or workable ranges, where the general conditions of a claim are disclosed in the prior art, involves only routing skill in the art, In re Alter, 105 USPQ 233 (CCPA 1955). Moreover, in the absence of any criticality (i.e. unobvious and/or unexpected result(s)), the parameter set forth above would have been obvious to a person having ordinary skill in the art at the time the invention was made, In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamanda in view of Tsuchi.
Regarding claims 6 and 14, Yamanda discloses all the features with respect to claim 1 as outlined above. Yamanda does not explicitly disclose wherein the buffer bias circuit comprises a floating current mirror, the floating current mirror comprising: a first NMOS transistor coupled in parallel with a first PMOS transistor, wherein a gate terminal of the NMOS transistor is coupled with an output of an N-bias circuit and a gate terminal of the PMOS transistor is coupled with an output of a P-bias circuit.
However, Tsuchi discloses wherein a buffer bias circuit [150/160, fig. 1] comprises a floating current mirror [160], the floating current mirror comprising: a first NMOS transistor [153] coupled in parallel with a first PMOS transistor [152], wherein a gate terminal of the NMOS transistor [gate of 153] is coupled with an output of an N-bias circuit [bias circuit output BN2] and a gate terminal of the PMOS transistor [gate 152] is coupled with an output of a P-bias circuit [bias circuit output BP2]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Yamanda by incorporating buffer/bias circuit as taught in Chen in order to provide biasing the transistors to minimize or eliminate over voltage.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Yamanda in view of Tsuchi further in view of Zhang et al (CN 202433801U and Zhang hereinafter).
Regarding claims 7 and 15, Yamanda in view of Tsuchi discloses all the features with respect to claim 6 and 14 as outlined above. Yamanda in view of Tsuchi does not explicitly disclose wherein the P-bias circuit comprises a current source, a second PMOS transistor, and a third PMOS transistor, wherein: the second PMOS transistor and the third PMOS transistor are configured as diode- connected transistors; the second PMOS transistor and the third PMOS transistor are coupled in series with a first operating voltage; the current source is coupled, at the output of the P-bias circuit, in series with the second PMOS transistor and the third PMOS transistor; the second PMOS transistor has a source-to-gate voltage temperature curve having a positive slope; and the third PMOS transistor has a source-to-gate voltage temperature curve having a negative slope.
However, Zhang discloses voltage circuit [fig. 2] comprises a current source [M1], a second PMOS transistor [M4], and a third PMOS transistor [M2], wherein: the second PMOS transistor and the third PMOS transistor are configured as diode-connected transistors; the second PMOS transistor and the third PMOS transistor are coupled in series with a first operating voltage [voltage VCC]; the current source is coupled, at the output of the P-bias circuit, in series with the second PMOS transistor and the third PMOS transistor; the second PMOS transistor has a source-to-gate voltage [M4 VGS] temperature curve having a positive slope [VREF3 is a positive temperature coefficient]; and the third PMOS transistor has a source- to-gate voltage [M2 VGS] temperature curve having a negative slope [VREF1 is a negative temperature coefficient]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Yamanda/ Tsuchi by incorporating bias circuit as taught in Zhang in order to provide stable threshold and bias voltage.
Regarding claims 8 and 16, Yamanda in view of Tsuchi further in view of Zhang discloses wherein the level shifting circuit comprises a source follower transistor [40a/40b, fig. 4] matched to the second PMOS transistor.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchi (US 20110298777) in view of Zhang et al. (CN 202433801U and Zhang hereinafter)
Regarding claim 17, Tsuchi discloses a voltage buffer [fig. 1], comprising: an input circuit [170] configured to receive an input voltage reference [V1], receive a feedback signal [output signal of 110 to gate 111], and generate an error signal [output of 170 at node N1 and N2] that corresponds to a difference between based on the feedback signal and the input voltage reference; an output circuit [110] comprising an output node [OUT node], wherein the output circuit is controllable to provide an output voltage [V0] at the output node; a feedback circuit [feedback from node 2 to gate 111 ] coupled with the output circuit and the input circuit, wherein the feedback circuit is configured to generate the feedback signal based on the output voltage [V0]; and a buffer bias circuit [150/160] coupled with the input circuit and the output circuit, wherein: the buffer bias circuit comprises a first NMOS transistor [153] coupled in parallel with a first PMOS transistor [152], wherein a gate terminal of the NMOS transistor [gate 153] is coupled with an N-bias circuit [bias circuit of BN2] and a gate terminal of the PMOS transistor [gate 152] is coupled with a P-bias circuit [bias circuit of BN2]. Tsuchi does not explicitly disclose the P-bias circuit comprises a diode-connected second PMOS transistor coupled in series with a diode-connected third PMOS transistor; the second PMOS transistor has a source-to-gate voltage temperature curve having a positive slope; and the third PMOS transistor has a source-to-gate voltage temperature curve having a negative slope.
However, Zhang discloses voltage circuit [fig. 2] comprises a diode-connected second
PMOS transistor [M4] coupled in series with a diode-connected third PMOS transistor [M2]; the
second PMOS transistor has a source-to-gate voltage [M4 VGS] temperature curve having a
positive slope [VREF3 is a positive temperature coefficient]; and the third PMOS transistor has a
source-to-gate voltage [M2 VGS] temperature curve having a negative slope [VREF1 is a
negative temperature coefficient]. It would have been obvious to one of ordinary skill in the art
before the effective filling date of the claimed invention was made to modify the invention of
Tsuchi by incorporating bias circuit as taught in Zhang in order to utilize known bias circuit output reference voltages in order to provide stable threshold and bias voltage.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchi in view of Zhang et al. further in view of Yamanda.
Regarding claim 18, Tsuchi in view of Zhang discloses all the features with respect to claim 17 as outlined above. Tsuchi in view of Zhang does not explicitly disclose a level shifting circuit, wherein: the buffer bias circuit is coupled to the output circuit through the level shifting circuit; and the level shifting circuit comprises a source follower transistor matched to the second PMOS transistor.
However, Yamanda discloses a level shifting circuit [40, 50, fig. 1], wherein: the buffer bias circuit [60] is coupled to the output circuit through the level shifting circuit; and the level shifting circuit comprises a source follower transistor [40a/40b, fig. 4] matched to the second PMOS transistor. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the invention of Tsuchi/ Zhang by incorporating level shifting circuit as taught in Yamanda in order to utilize known level shifter.
Regarding claim 19, Tsuchi in view of Zhang further in view of Yamanda discloses the input circuit is operable in a second voltage domain [V2]; and the level shifting circuit and the output circuit are operable in a first voltage domain [V1], wherein the first voltage domain comprises a first voltage level and the second voltage domain comprises a second voltage level, wherein the second voltage level is less than the first voltage level.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tsuchi in view of Zhang et al. and Yamanda further in view of Bogner.
Regarding claim 20, Tsuchi in view of Zhang further in view of Yamanda discloses all the features with respect to claim 19 as outlined above. Tsuchi in view of Zhang further in view of Yamanda further discloses wherein: the input circuit comprise one or more transistors [fig. 1, Tsuchi], the second voltage domain comprises a second operating voltage [operating voltage of +V2] less than or equal to a rated operational voltage limit of the one or more transistors [inherent: 10/40 uses transistors rated for vdd1 and intermediate voltage]. Tsuchi in view of Zhang further in view of Yamanda does not explicitly disclose the first voltage domain comprises a first operating voltage greater than the rated operational voltage limit of the one or more transistors, wherein the rated operational voltage limit is a foundry-recommended voltage limit.
However, Bogner discloses maximum voltage level of the input voltage is higher than the applicable operational voltage [abstract, [0006]]. It would have been obvious to one of ordinary skill in the art before the effective filing date to select a voltage greater than the rated operational voltage limit for the desire performance and manufacturing specified voltage limit as taught in Bogner the use of manufacturing specified voltage limit would have been an obvious design choice or routine parameter selection.
Response to Arguments
Applicant's arguments filed 08/26/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 9, applicant argues that Yamanda fails to disclose “a buffer bias circuit "coupled with the input circuit" and "configured to provide a bias signal" that is adjusted by the error signal, and a level shifting circuit "coupled with the buffer bias circuit and the output circuit," "configured to translate the adjusted bias signal from the second voltage domain to the first voltage domain." wherein the buffer bias circuit is coupled between the input circuit and the level shifting circuit. Claim 9 recites a similar set of features and coupling.
However, Yamanda discloses the buffer bias circuit [60 including Q3 and Q4 of 50] is between input circuit [10] and level shifting circuit [40 and 50] because it provides the bias conditions required for level shift circuit 40 to operate on the output of circuit 10. The buffer bias is functionally between the input circuit /error amplifier and level shifting circuit. Applicant further argues that 40 and 50 are not level shifting circuits are contradicted by the specification/drawing, which identifies the circuits 40/50 current-voltage conversion stage performing converts a bias current into collector voltage at nodes 40a/40b, which resides in a different voltage domain than the input amplifier. This is level shifting. Furthermore, circuit 50 translate the voltage at nodes 40a/40b into the +/- V2 domain required to drive the output transistors. Thus, both circuits 40/50 perform level shifting function as claimed.
Regarding claim 2, applicant argues that Bogner does not teach that its transistors are operated above an applicable operational voltage. Applicant’s argument is not persuasive. Bonger teaches that “a switching circuit maximum voltage level of the input voltage is higher than the applicable operational voltage” [abstract, par. [0006]. The input voltage used during switching constitutes an operating voltage, and Bonger teaches that this operating voltage exceeds the rated operational voltage.
Regarding claim 17, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, the combination of Tsuchi and Zhang discloses would suggest that any person ordinary skill in the art would use known bias circuit in order to provide a reference voltage with stable threshold and bias voltage.
Conclusion
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/METASEBIA T RETEBO/Primary Examiner, Art Unit 2836
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