DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 4-11 and 14-21 are objected to because of the following informalities:
Claim 4 (claim 14) recites “each pair of dielectric layers” which should be replaced with “each pair of the one or more pairs of dielectric layers”, to avoid antecedent basis issue.
Claim 6 (claims 8, 10-11, 16, 18, and 20-21) recites “the other” which should be replaced with “another”, to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8, 11-18, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0074195 to Kim et al. (hereinafter Kim) in view of Yoo (US 2018/0240804).
With respect to claim 1, Kim discloses a semiconductor memory device (e.g., NAND flash memory device) (Kim, Figs. 2-4, ¶0028-¶0057), comprising:
a data storage layer (134) (Kim, Figs. 3-4, ¶0034-¶0037);
a word line (e.g., conductive patterns CL including word lines WL1, WL2,…,WLn-1) (Kim, Figs. 3-4, ¶0032, ¶0034, ¶0053) overlapping with the data storage layer (134); and
a blocking insulating layer (132A) (Kim, Figs. 3-4, ¶0043-¶0046, ¶0048) interposed between the data storage layer (134) and the word line (CL/WL).
Further, Kim does not specifically disclose the blocking insulating layer comprising a superlattice structure.
However, Kim teaches that the blocking insulating layer (134) (Kim, Figs. 3-4, ¶0046) includes a combination of metal oxides having a higher dielectric constant than silicon oxide and including hafnium oxide and zirconium oxide.
Further, Yoo teaches forming a nonvolatile memory device (Yoo, Figs. 1-2, ¶0005-¶0006, ¶0015-¶0040, ¶0071) comprising a high dielectric constant insulating layer between the semiconductor channel (101) and the gate electrode layer (155) and including ferroelectric superlattice structure (10) (Yoo, Figs. 1-2, ¶0018, ¶0022-¶0023, ¶0037) comprising different dielectric layers alternatively layered, wherein the ferroelectric properties of the superlattice structure are controlled through anisotropic stress in the interface regions between the dielectric layers with different compositions. The superlattice structure (10) includes hafnium oxide layers (125a, 125b, and 125c) and zirconium oxide layers (135a, 135b, 135c), to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim by forming the blocking insulating layer including a combination of metal oxides having a higher dielectric constant than silicon oxide, wherein the combination of metal oxides includes a superlattice structure comprising different dielectric layers alternatively layered a taught by Yoo to have the semiconductor memory device, comprising: the blocking insulating layer comprising a superlattice structure, in order to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
Regarding claim 2, Kim in view of Yoo discloses the semiconductor memory device of claim 1. Further, Kim discloses the semiconductor memory device, further comprising: a channel layer (150) (Kim, Figs. 3-4, ¶0033-¶0037, ¶0043-¶0046) overlapping with the word line (CL/WL), the blocking insulating layer (132A) and data storage layer (134) interposed between the word line (CL/WL) and the channel layer (150).
Regarding claim 3, Kim in view of Yoo discloses the semiconductor memory device of claim 1. Further, Kim discloses the semiconductor memory device, further comprising: a tunnel insulating layer (140) (Kim, Figs. 3-4, ¶0036-¶0037, ¶0043-¶0046) overlapping with the word line (CL/WL), the blocking insulating layer (132) and data storage layer (134) interposed between the word line (CL/WL) and the tunnel insulating layer (140).
Regarding claims 4-8 and 11, Kim in view of Yoo discloses the semiconductor memory device of claim 1. Further, Kim discloses the semiconductor memory device, wherein the blocking insulating layer (132) (Kim, Figs. 3-4, ¶0046) includes one or more of dielectric layers, each of dielectric layers comprising a first dielectric layer (e.g., hafnium oxide) and a second dielectric layer (e.g., zirconium oxide) disposed in a direction from the data storage layer (134) towards the word line (CL/WL), but does not specifically disclose one or more pairs of dielectric layers, each pair of dielectric layers comprising a first dielectric layer and a second dielectric layer disposed in a direction towards the word line (as claimed in claim 4); wherein each of the first dielectric layer and the second dielectric layer includes a crystalline oxide (as claimed in claim 5); wherein one of the first dielectric layer and the second dielectric layer includes a ferroelectric material and the other includes an antiferroelectric material (as claimed in claim 6); wherein the first dielectric layer includes a different crystalline phase from the second dielectric layer (as claimed in claim 7); wherein one of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase and the other includes a tetragonal crystalline phase (as claimed in claim 8); wherein one of the first dielectric layer and the second dielectric layer includes a hafnium oxide (HfO2) layer and the other includes a zirconium oxide (ZrO2) layer (as claimed in claim 11).
However, Yoo teaches forming the superlattice structure (10) including one or more pairs (e.g., unit-stacks 10a/10b/10c) (Yoo, Figs. 1-2, ¶0025, ¶0037) of dielectric layers (125a/135a, 125b/135b, and 125c/135c), each pair of dielectric layers comprising a first dielectric layer (125a, 125b, 125c) and a second dielectric layer (135a, 135b, 135c) disposed in a direction towards the gate electrode (155), wherein each of the first dielectric layer (125a, 125b, 125c) and the second dielectric layer (135a, 135b, 135c) includes a crystalline oxide (e.g., having tetragonal crystal system or orthorhombic crystal system) (Yoo, Figs. 1-2, ¶0015, ¶0034); wherein one of the first dielectric layer and the second dielectric layer includes a ferroelectric material (e.g., zirconium oxide) and the other includes an antiferroelectric material (e.g., non-ferroelectric hafnium oxide) (Yoo, Figs. 1-2, ¶0015); wherein the first dielectric layer includes a different crystalline phase from the second dielectric layer (e.g., non-ferroelectric hafnium oxide has tetragonal crystal system and zirconium oxide has orthorhombic crystal system); wherein one of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase (e.g., zirconium oxide) and the other includes a tetragonal crystalline phase (e.g., hafnium oxide) (Yoo, Figs. 1-2, ¶0015, ¶0034); wherein one of the first dielectric layer (125a, 125b, 125c) and the second dielectric layer (135a, 135b, 135c) includes a hafnium oxide (HfO2) layer and the other includes a zirconium oxide (ZrO2) layer, to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim/Yoo by forming the blocking insulating layer including a combination of metal oxides having different crystalline phases, wherein the combination of metal oxides includes a superlattice structure comprising different dielectric layers alternatively layered a taught by Yoo to have the semiconductor memory device, wherein one or more pairs of dielectric layers, each pair of dielectric layers comprising a first dielectric layer and a second dielectric layer disposed in a direction towards the word line (as claimed in claim 4); wherein each of the first dielectric layer and the second dielectric layer includes a crystalline oxide (as claimed in claim 5); wherein one of the first dielectric layer and the second dielectric layer includes a ferroelectric material and the other includes an antiferroelectric material (as claimed in claim 6); wherein the first dielectric layer includes a different crystalline phase from the second dielectric layer (as claimed in claim 7); wherein one of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase and the other includes a tetragonal crystalline phase (as claimed in claim 8); wherein one of the first dielectric layer and the second dielectric layer includes a hafnium oxide (HfO2) layer and the other includes a zirconium oxide (ZrO2) layer (as claimed in claim 11), in order to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
Regarding claim 12, Kim in view of Yoo discloses the semiconductor memory device of claim 1. Further, Kim does not specifically disclose that the blocking insulating layer includes first dielectric layers and second dielectric layers, the first dielectric layers alternately stacked with the second dielectric layers, and wherein at least one of the first dielectric layers comprises a different number of monomolecular layers than at least one of the second dielectric layers.
However, Yoo teaches forming the superlattice structure (10) including one or more pairs (e.g., unit-stacks 10a/10b/10c) (Yoo, Figs. 1-2, ¶0025-¶0027) of dielectric layers (125a/135a, 125b/135b, and 125c/135c), each pair of dielectric layers comprising a first dielectric layer (125a, 125b, 125c) and a second dielectric layer (135a, 135b, 135c) such that the superlattice structure (10) includes first dielectric layers (125a, 125b, 125c) and second dielectric layers (135a, 135b, 135c), the first dielectric layers (125a, 125b, 125c) alternately stacked with the second dielectric layers (135a, 135b, 135c) and each includes a plurality of monolayers (Yoo, Figs. 1-2, ¶0026-¶0027), and thickness of the first dielectric layers (125a, 125b, 125c) and the second dielectric layers (135a, 135b, 135c) individually varied to achieve the desired thickness of the superlattice (Yoo, Figs. 1-2, ¶0027).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim/Yoo by forming the blocking insulating layer including a superlattice structure comprising different dielectric layers alternatively layered and each having a plurality of monolayers as taught by Yoo, wherein thicknesses of the different dielectric layers of the superlattice individually varied to have the semiconductor memory device, wherein the blocking insulating layer includes first dielectric layers and second dielectric layers, the first dielectric layers alternately stacked with the second dielectric layers, and wherein at least one of the first dielectric layers comprises a different number of monomolecular layers than at least one of the second dielectric layers, in order to provide structurally stable ferroelectric material layer having the desired thickness and with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0027, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
With respect to claim 13, Kim discloses a semiconductor memory device (e.g., NAND flash memory device) (Kim, Figs. 2-4, ¶0028-¶0057), comprising:
a plurality of word lines (e.g., conductive patterns CL including word lines WL1, WL2,…,WLn-1) (Kim, Figs. 3-4, ¶0032, ¶0034, ¶0053) stacked separately from each other;
a channel layer (150) (Kim, Figs. 3-4, ¶0033-¶0037, ¶0043-¶0046) extending in a stacking direction of the plurality of word lines (WL1, WL2,…,WLn-1) to penetrate the plurality of word lines;
a blocking insulating layer (132A) (Kim, Figs. 3-4, ¶0043-¶0046, ¶0048) interposed between the channel layer (150) and each of the plurality of word lines (WL1, WL2,…,WLn-1);
a data storage layer (134) (Kim, Figs. 3-4, ¶0034-¶0037) interposed between the channel layer (150) and the blocking insulating layer (132A); and
a tunnel insulating layer (140) interposed between the channel layer (150) and the data storage layer (134).
Further, Kim does not specifically disclose that the blocking insulating layer includes a superlattice structure.
However, Kim teaches that the blocking insulating layer (134) (Kim, Figs. 3-4, ¶0046) includes a combination of metal oxides having a higher dielectric constant than silicon oxide and including hafnium oxide and zirconium oxide.
Further, Yoo teaches forming a nonvolatile memory device (Yoo, Figs. 1-2, ¶0005-¶0006, ¶0015-¶0040, ¶0071) comprising a high dielectric constant insulating layer between the semiconductor channel (101) and the gate electrode layer (155) and including ferroelectric superlattice structure (10) (Yoo, Figs. 1-2, ¶0018, ¶0022-¶0023, ¶0037) comprising different dielectric layers alternatively layered, wherein the ferroelectric properties of the superlattice structure are controlled through anisotropic stress in the interface regions between the dielectric layers with different compositions. The superlattice structure (10) includes hafnium oxide layers (125a, 125b, and 125c) and zirconium oxide layers (135a, 135b, 135c), to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim by forming the blocking insulating layer including a combination of metal oxides having a higher dielectric constant than silicon oxide, wherein the combination of metal oxides includes a superlattice structure comprising different dielectric layers alternatively layered a taught by Yoo to have the semiconductor memory device, wherein the blocking insulating layer includes a superlattice structure, in order to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
Regarding claims 14-18 and 21, Kim in view of Yoo discloses the semiconductor memory device of claim 13. Further, Kim discloses the semiconductor memory device, wherein the blocking insulating layer (132) (Kim, Figs. 3-4, ¶0046) includes one or more of dielectric layers, each of dielectric layers comprising a first dielectric layer (e.g., hafnium oxide) and a second dielectric layer (e.g., zirconium oxide) disposed in a direction from the data storage layer (134) towards the plurality of word lines (CL/WL), but does not specifically disclose one or more pairs of dielectric layers, each pair of dielectric layers comprising a first dielectric layer and a second dielectric layer disposed in a direction towards the plurality of word lines (as claimed in claim 14); wherein each of the first dielectric layer and the second dielectric layer includes a crystalline oxide (as claimed in claim 15); wherein one of the first dielectric layer and the second dielectric layer includes a ferroelectric material and the other includes an antiferroelectric material (as claimed in claim 16); wherein the first dielectric layer includes a different crystalline phase from the second dielectric layer (as claimed in claim 17); wherein one of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase and the other includes a tetragonal crystalline phase (as claimed in claim 18); wherein one of the first dielectric layer and the second dielectric layer includes a hafnium oxide (HfO2) layer and the other includes a zirconium oxide (ZrO2) layer (as claimed in claim 21).
However, Yoo teaches forming the superlattice structure (10) including one or more pairs (e.g., unit-stacks 10a/10b/10c) (Yoo, Figs. 1-2, ¶0025, ¶0037) of dielectric layers (125a/135a, 125b/135b, and 125c/135c), each pair of dielectric layers comprising a first dielectric layer (125a, 125b, 125c) and a second dielectric layer (135a, 135b, 135c) disposed in a direction towards the gate electrode (155), wherein each of the first dielectric layer (125a, 125b, 125c) and the second dielectric layer (135a, 135b, 135c) includes a crystalline oxide (e.g., having tetragonal crystal system or orthorhombic crystal system) (Yoo, Figs. 1-2, ¶0015, ¶0034); wherein one of the first dielectric layer and the second dielectric layer includes a ferroelectric material (e.g., zirconium oxide) and the other includes an antiferroelectric material (e.g., non-ferroelectric hafnium oxide) (Yoo, Figs. 1-2, ¶0015); wherein the first dielectric layer includes a different crystalline phase from the second dielectric layer (e.g., non-ferroelectric hafnium oxide has tetragonal crystal system and zirconium oxide has orthorhombic crystal system); wherein one of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase (e.g., zirconium oxide) and the other includes a tetragonal crystalline phase (e.g., hafnium oxide) (Yoo, Figs. 1-2, ¶0015, ¶0034); wherein one of the first dielectric layer (125a, 125b, 125c) and the second dielectric layer (135a, 135b, 135c) includes a hafnium oxide (HfO2) layer and the other includes a zirconium oxide (ZrO2) layer, to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim/Yoo by forming the blocking insulating layer including a combination of metal oxides having different crystalline phases, wherein the combination of metal oxides includes a superlattice structure comprising different dielectric layers alternatively layered a taught by Yoo to have the semiconductor memory device, wherein one or more pairs of dielectric layers, each pair of dielectric layers comprising a first dielectric layer and a second dielectric layer disposed in a direction towards the plurality of word lines (as claimed in claim 14); wherein each of the first dielectric layer and the second dielectric layer includes a crystalline oxide (as claimed in claim 15); wherein one of the first dielectric layer and the second dielectric layer includes a ferroelectric material and the other includes an antiferroelectric material (as claimed in claim 16); wherein the first dielectric layer includes a different crystalline phase from the second dielectric layer (as claimed in claim 17); wherein one of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase and the other includes a tetragonal crystalline phase (as claimed in claim 18); wherein one of the first dielectric layer and the second dielectric layer includes a hafnium oxide (HfO2) layer and the other includes a zirconium oxide (ZrO2) layer (as claimed in claim 21), in order to provide structurally stable ferroelectric material layer with controlled ferroelectric properties by anisotropic stress (Yoo, ¶0005-¶0006, ¶0017, ¶0023, ¶0034-¶0035, ¶0038-¶0039, ¶0071).
Claims 9-10 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2024/0074195 to Kim in view of Yoo (US 2018/0240804) as applied to claim 4, and further in view of Nishida et al. (US 2017/0103988, hereinafter Nishida).
Regarding claims 9-10 and 19-20, Kim in view of Yoo discloses the semiconductor memory device of claim 4 (claim 14). Further, Kim does not specifically disclose the semiconductor memory device, wherein the first dielectric layer includes a different crystalline phase distribution from the second dielectric layer (as claimed in claims 9 and 19); wherein each of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase, a tetragonal crystalline phase, and a monoclinic crystalline phase, and wherein one of the first dielectric layer and the second dielectric layer includes the orthorhombic crystalline phase more than the tetragonal crystalline phase and the monoclinic crystalline phase, and the other includes the tetragonal crystalline phase more than the orthorhombic crystalline phase and the monoclinic crystalline phase (as claimed in claims 10 and 20).
However, Nishida teaches forming a ferroelectric film (Nishida, Figs. 1-2, ¶0007-¶0008, ¶0021, ¶0023, ¶0026, ¶0034-¶0036, ¶0040-¶0047) including a plurality of layers with different crystalline structures to improve the ferroelectric behavior of the film. The layers of the ferroelectric film are differentiated based on differences in volume of a lattice cell. Such differences result from processing used to crystallize the film or by the materials used to form the film. For example, different crystalline structures are formed by introducing different types or concentrations of dopant in different layers of the film. Different crystal phases (e.g., monoclinic, tetragonal, orthorhombic, cubic) exist in a ferroelectric film (Nishida, Figs. 1-2, ¶0034), and a ferroelectric material has a higher proportion or ratio of one crystal phase over other crystal phases of the material. For hafnium oxide, the orthorhombic crystal phase exhibits improved ferroelectric properties over some of the other phases, such as monoclinic, tetragonal, and cubic (Nishida, Figs. 1-2, ¶0035). The desired dopant distribution provides a crystalline structure of the film to have a crystalline phase that provides certain ferroelectric properties of the film. The layers of the ferroelectric film doped with different dopants would have different lattice volumes that provides a suitable level of strain within the crystalline structure such that the crystalline structure has an orthorhombic phase (Nishida, Figs. 1-2, ¶0041). The distribution of dopants across the plurality of layers (e.g., 210-240) (Nishida, Fig. 2, ¶0045) promotes one or more crystalline structures to have an orthorhombic phase such that a larger proportion of crystalline structures have an orthorhombic phase over other phases (e.g., monoclinic, tetragonal, cubic).
Thus, Nishida recognizes that types and concentrations of dopants in different layers of the film impacts lattice volumes and crystalline structure of the layers of the film to provide a dominant crystalline phase to improve the ferroelectric behavior of the film. Thus, types and concentrations of dopants in different layers of the film are result-effective variables.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, types and concentrations of dopants in different dielectric layers as Nishida has identified types and concentrations of dopants in different dielectric layers as result-effective variables. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at the first dielectric layer includes a different crystalline phase distribution from the second dielectric layer; wherein each of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase, a tetragonal crystalline phase, and a monoclinic crystalline phase, and wherein one of the first dielectric layer and the second dielectric layer includes the orthorhombic crystalline phase more than the tetragonal crystalline phase and the monoclinic crystalline phase, and the other includes the tetragonal crystalline phase more than the orthorhombic crystalline phase and the monoclinic crystalline phase, in order to obtain the first and second dielectric layers having different lattice volumes that provides a suitable level of strain within the crystalline structure of the film including the first and second dielectric layers such that the crystalline structure of the film has a dominant orthorhombic phase, as taught by Nishida (¶0034-¶0036, ¶0041, ¶0045) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor memory device of Kim/Yoo by optimizing type and dopant concentration within the first and second dielectric layers as taught by Nishida to have the semiconductor memory device, wherein the first dielectric layer includes a different crystalline phase distribution from the second dielectric layer (as claimed in claim 9); wherein each of the first dielectric layer and the second dielectric layer includes an orthorhombic crystalline phase, a tetragonal crystalline phase, and a monoclinic crystalline phase, and wherein one of the first dielectric layer and the second dielectric layer includes the orthorhombic crystalline phase more than the tetragonal crystalline phase and the monoclinic crystalline phase, and the other includes the tetragonal crystalline phase more than the orthorhombic crystalline phase and the monoclinic crystalline phase (as claimed in claim 10), in order to improve the ferroelectric behavior of the ferroelectric film to obtain a memory device having smaller dimensions, higher density, and desired performance characteristics (Nishida, ¶0007-¶0008, ¶0021, ¶0023, ¶0034-¶0036, ¶0041, ¶0045).
Conclusion
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/NATALIA A GONDARENKO/ Primary Examiner, Art Unit 2891
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