DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the pending claims have been considered as to the point that Voronin et al. (US 2018/0138018), Huang et al. (US 2024/0003010), and Mu et al. (US 5,612,254) do not teach that the dielectric covers the edge of the substrate but are moot based on the new grounds of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 and 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Voronin et al. (U.S. Patent Application Publication 2018/0138018, hereafter Voronin ‘018) in view of Huang et al. (U.S. Patent Application Publication 2024/0003010, hereafter Huang ‘010) and Tran Quoc (U.S. Patent Application Publication 2007/0004220, hereafter Tran Quoc ‘220).
Claim 1: Voronin ‘018 teaches a method for processing a substrate (abstract, [0001]) comprising:
providing a plasma enhanced chemical vapor deposition chamber (Fig. 6, [0050]) comprising sidewall gas inlets (659) disposed on sidewalls of the PECVD chamber (Fig. 6, [0061]) and a top gas inlet (653) disposed on a top plate of the PECVD chamber (Fig. 6, [0060]);
receiving the substrate (110) on a substrate holder (612) within the PECVD chamber (Fig. 6, [0051]);
flowing a precursor gas into the PECVD chamber through the sidewall gas inlets at a first flow rate and the top gas inlet at a second flow rate (Fig. 6, [0060], [0061]);
applying a source power to the top plate to form a plasma from the precursor gas ([0054]); and
exposing the substrate to the plasma to deposit a layer over the substrate ([0026], [0050]).
Voronin ‘018 further teaches that the method is for semiconductor device manufacturing ([0001]).
With respect to claim 1, Voronin ‘018 does not explicitly teach that the layer is a dielectric layer, that the dielectric layer covers the edges of the substrate, or that the layer has an edge thickness and a center thickness wherein the edge thickness is different from the center thickness.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract, [0057]). Huang ‘010 teaches that the deposited layer can be silicon nitride, which is a dielectric, with an edge thickness that is different from the center thickness ([0055], [0057]). Huang ‘010 teaches that this allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing (abstract, [0002], [0004], [0055]). Both Huang ‘010 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘010, abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the deposited layer of silicon nitride with an edge thickness that is different from the center thickness taught by Huang ‘010 as the deposited layer in the method taught by Voronin ‘018 because it allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing, as taught by Huang ‘010.
With respect to claim 1, the modified teachings of Voronin ‘018 do not explicitly teach that the dielectric layer covers the edges of the substrate.
Tran Quoc ‘220 teaches a semiconductor device manufacturing method ([0001]) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract) where the layer can be a dielectric layer (abstract). Tran Quoc ‘220 teaches that the dielectric layer can cover the edges of the substrate (Fig. 3, [0023], [0026], [0064]). Tran Quoc ‘220 teaches that this decreases the amount of etching radicals on the periphery of the substrate to allow substantially equal etching across the substrate surface ([0014], [0015]). Both Tran Quoc ‘220 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘220, [0001]) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘220, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric layer cover the edges of the substrate as taught by Tan Quoc ‘220 in the method taught by the modified teachings of Voronin ‘018 because this decreases the amount of etching radicals on the periphery of the substrate to allow substantially equal etching across the substrate surface, as taught by Tran Quoc ‘220.
Claim 2: Voronin ‘010 teaches that the source power can be microwave power comprising a microwave frequency ([0012]), the top plate can comprise quartz ([0054]), and the source power can be applied to a radial line slot antenna ([0020]) at a power level of up to 5000 watts ([0011]).
With respect to claim 2, the modified teachings of Voronin ‘010 do not explicitly teach that the power level is between 500 W and 5000 W. However, the claimed power range of between 500 W and 5000 W is obvious over the power range of up to 5000 W taught by Voronin ‘010 because they overlap. See MPEP 2144.05.
Claim 3: Voronin ‘010 teaches that the first flow rate through the sidewall gas inlets and the second flow rate through the top gas inlet are controlled to control plasma stability ([0002], [0042], [0060], [0061]).
With respect to claim 3, the modified teachings of Voronin ‘010 do not explicitly teach that the first flow rate is faster than the second flow rate.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the first and second flow rates, and, therefore, the first and second flow rates relative values, in the method taught by the modified teachings of Voronin ‘010 because the first and second flow rates affect plasma stability, as taught by Voronin ‘010.
With respect to claim 3, the modified teachings of Voronin ‘010 do not explicitly teach that the edge thickness is larger than the center thickness and that a thickness ratio of the edge thickness to the center thickness is between 1.5:1 and 3.5:1.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract, [0057]). Huang ‘010 teaches that the deposited layer can have an edge thickness that is larger than the center thickness ([0055], [0057]). Huang ‘010 teaches that this allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing (abstract, [0002], [0004], [0055]). Huang ‘010 further teaches that the thickness profile, and therefore ratio of edge thickness to center thickness, affects the deposited layer’s ability to compensate asymmetric bowing the substrate ([0062]). Both Huang ‘010 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘010, abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the deposited layer have an edge thickness that is larger than the center thickness as taught by Huang ‘010 in the method taught by the modified teachings of Voronin ‘018 because it allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing, as taught by Huang ‘010.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ratio of the edge thickness to center thickness in the method taught by the modified teachings of Voronin ‘018 because the thickness profile, and therefore ratio of edge thickness to center thickness, affects the deposited layer’s ability to compensate asymmetric bowing the substrate, as taught by Huang ‘010.
Claim 4: Voronin ‘010 teaches that the first flow rate through the sidewall gas inlets and the second flow rate through the top gas inlet are controlled to control plasma stability ([0002], [0042], [0060], [0061]).
With respect to claim 4, the modified teachings of Voronin ‘010 do not explicitly teach that the first flow rate is slower than the second flow rate.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the first and second flow rates, and, therefore, the first and second flow rates relative values, in the method taught by the modified teachings of Voronin ‘010 because the first and second flow rates affect plasma stability, as taught by Voronin ‘010.
With respect to claim 4, the modified teachings of Voronin ‘010 do not explicitly teach that the edge thickness is smaller than the center thickness or that a thickness ratio of the edge thickness to the center thickness is between 1:1.5 and 1:3.5.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract, [0057]). Huang ‘010 teaches that the deposited layer can have an edge thickness that is smaller than the center thickness ([0055], [0057]). Huang ‘010 teaches that this allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing (abstract, [0002], [0004], [0055]). Huang ‘010 further teaches that the thickness profile, and therefore ratio of edge thickness to center thickness, affects the deposited layer’s ability to compensate asymmetric bowing the substrate ([0062]). Both Huang ‘010 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘010, abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the deposited layer have an edge thickness that is smaller than the center thickness as taught by Huang ‘010 in the method taught by the modified teachings of Voronin ‘018 because it allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing, as taught by Huang ‘010.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ratio of the edge thickness to center thickness in the method taught by the modified teachings of Voronin ‘018 because the thickness profile, and therefore ratio of edge thickness to center thickness, affects the deposited layer’s ability to compensate asymmetric bowing the substrate, as taught by Huang ‘010.
Claim 5: Voronin ‘018 teaches that the substrate can be a silicon wafer ([0018]). The modified teachings of Voronin ‘018 teach that the deposited layer can be silicon nitride, as discussed above.
With respect to claim 5, the modified teachings of Voronin ‘018 do not explicitly teach that the precursor gas comprises at least one of silane, disilane, ammonia, hydrogen gas, nitrogen gas, and nitrous oxide.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract, [0057]) where the deposited layer is silicon nitride ([0060]). Huang ‘010 teaches that the precursor for the silicon nitride can comprise ammonia ([0060]). Both Huang ‘010 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘010, abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the ammonia taught by Huang ‘010 in the precursor gas in the modified teachings of Voronin ‘018 because it is a suitable precursor gas for silicon nitride deposition, as taught by Huang ‘010.
Claim 8: Voronin ‘018 teaches that the method can further comprise controlling a temperature of the substrate holder to maintain a substrate temperature during plasma deposition ([0052]).
Claim 9: Voronin ‘018 teaches that the deposition can be performed without a focus ring or clamp (Fig. 1, [0015]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Voronin et al. ‘018 in view of Huang et al. ‘010 and Tran Quoc ‘220 as applied to claim 1 above, and further in view of Hyeong et al. (KR 20240003033 A, hereafter Hyeong ‘033, with machine translation).
The modified teachings of Voronin ‘018 teach the limitations of claim 1, as discussed above. The modified teachings of Voronin ‘018 teach that the edge thickness and center thickness of the deposited layer are different, as discussed above.
With respect to claim 6, they do not explicitly teach that the top plate is a gas shower head comprising a plurality of concentric rings, each concentric ring comprising a plurality of gas nozzles, or that flow rates through each concentric ring may be controlled.
Hyeong ‘033 teaches a semiconductor device manufacturing method ([0002]) comprising depositing a layer by plasma enhanced chemical vapor deposition ([0002]). Hyeong ‘033 teaches that the top plate of the deposition chamber can be a gas shower head (Fig. 3, [0002]) comprising an inner ring (210) and outer ring (230) which are concentric (Fig. 3, [0041]), where each ring comprises a plurality of gas nozzles (Fig. 3) and flow rate through each ring can be controlled (Fig. 3, [0062]). Hyeong ‘033 teaches that this allows for control of thickness variation in the deposited film ([0062]). Both Hyeong ‘033 and Voronin ‘018 teach semiconductor device manufacturing methods (‘018, [0001]; ‘033, [0002]) comprising depositing a layer by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘033, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the top plate comprising a gas shower head comprising an inner ring and outer ring which are concentric where each ring comprises a plurality of gas nozzles and flow rate through each ring can be controlled taught by Hyeong ‘033 as the top plate in the method taught by the modified teachings of Voronin ‘018 because it allows for control of thickness variation in the deposited film, as taught by Hyeong ‘033.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Voronin et al. ‘018 in view of Huang et al. ‘010 and Tran Quoc ‘220 as applied to claim 1 above, and further in view of Shek et al. (U.S. Patent Application Publication 2021/0189555, hereafter Shek ‘555).
The modified teachings of Voronin ‘018 teach the limitations of claim 1, as discussed above. Voronin ‘018 further teaches that the sidewall gas inlets can comprise a first gas inlet and a second gas inlet disposed on opposite sidewalls of the chamber (Fig. 6).
With respect to claim 7, the modified teachings of Voronin ‘018 do not explicitly teach that the substrate is spun about a center axis during exposing to plasma.
Shek ‘555 teaches a method of manufacturing a semiconductor device (abstract, [0005]) comprising plasma enhanced chemical vapor deposition (abstract). Shek ‘555 teaches that the substrate can be rotated about the central axis during exposure to the deposition plasma ([0073]). Shek ‘555 teaches that this rotation minimizes the effect of local variability in gas flow geometries ([0073]). Both Shek ‘555 and Voronin ‘018 teach methods of manufacturing a semiconductor device (‘018, [0001]; ‘555, abstract, [0005]) comprising plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘555, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rotate the substrate about the central axis during exposure to the deposition plasma as taught by Shek ‘555 in the method taught by the modified teachings of Voronin ‘018 because this rotation minimizes the effect of local variability in gas flow geometries, as taught by Shek ‘555.
Claim(s) 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mu et al. (U.S. Patent 5,612,254, hereafter Mu ‘254) in view of Huang et al. ‘010 and Tran Quoc ‘220.
Claim 10: Mu ‘254 teaches a method of processing a substrate (abstract) comprising:
depositing a first dielectric layer (23) on a substrate (22, 20) (Fig. 2, col 5 ln 52-col 6 ln 7);
depositing a second dielectric layer (50) over the first dielectric layer with a uniform thickness (Fig. 5, col 6 ln 34-63);
depositing a photoresist, which corresponds to the claimed mask layer, over the second dielectric layer (col 6 ln 34-63);
patterning the photoresist to form a patterned photoresist comprising a feature pattern (col 6 ln 34-63); and
etching the substrate to form feature openings corresponding to the feature pattern (Fig. 5, col 6 ln 34-63).
Mu ‘254 further teaches that the method can be for semiconductor device manufacturing (abstract) and the first dielectric can be silicon nitride (abstract, col 5 ln 52-col 6 ln 7).
With respect to claim 10, Mu ‘254 does not explicitly teach that the first dielectric layer has an edge thickness and a center thickness wherein the center thickness is less than the edge thickness, that the first dielectric covers edges of the substrate, or that the edge thickness of the first dielectric layer protects the edges of the substrate during etching.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a silicon nitride layer (abstract, [0057]). Huang ‘010 teaches that the deposited silicon nitride can have an center thickness that is less than the edge thickness ([0055], [0057]). Huang ‘010 teaches that this allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing (abstract, [0002], [0004], [0055]). Both Huang ‘010 and Mu ‘254 teach semiconductor device manufacturing methods (‘254, abstract; ‘010, abstract) comprising depositing a silicon nitride layer (‘254, abstract, col 5 ln 52-col 6 ln 7; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the deposited silicon nitride layer have a center thickness that is less than the edge thickness as taught by Huang ‘010 in the method taught by Mu ‘254 because it allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing, as taught by Huang ‘010.
With respect to claim 10, the modified teachings of Mu ‘254 do not explicitly teach that that the first dielectric covers edges of the substrate, or that the edge thickness of the first dielectric layer protects the edges of the substrate during etching.
Tran Quoc ‘220 teaches a semiconductor device manufacturing method ([0001]) comprising depositing a dielectric layer (abstract). Tran Quoc ‘220 teaches that the dielectric layer can cover the edges of the substrate (Fig. 3, [0023], [0026], [0064]). Tran Quoc ‘220 teaches that this decreases the amount of etching radicals on the periphery of the substrate to allow substantially equal etching across the substrate surface ([0014], [0015]). Both Tran Quoc ‘220 and Mu ‘254 teach semiconductor device manufacturing methods (‘254, abstract; ‘220, [0001]) comprising depositing a dielectric layer (‘254, abstract, col 5 ln 52-col 6 ln 7; ‘220, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric layer cover the edges of the substrate as taught by Tan Quoc ‘220 in the method taught by the modified teachings of Mu ‘254 because this decreases the amount of etching radicals on the periphery of the substrate to allow substantially equal etching across the substrate surface, as taught by Tran Quoc ‘220.
The dielectric layer covering the edges of the substrate decreases the amount of etching radicals, as discussed above. Therefore, the dielectric layer covering the edges provides protection during the etching.
Claim 11: Mu ‘254 teaches that the substrate can comprise a silicon wafer (col 5 ln 52-col 6 ln 7), the first dielectric layer can comprise silicon nitride (col 5 ln 52-col 6 ln 7), the second dielectric layer can comprise silicon oxide (col 6 ln 34-63), and the feature openings can comprise through vias (Fig. 5, col 6 ln 34-63).
Claim 12: Mu ‘254 teaches performing chemical mechanical polishing steps where performing the chemical mechanical polishing steps on the layers forms substantially planar surfaces (col 3 ln 17-31).
With respect to claim 12, the modified teachings of Mu ‘254 do not explicitly teach that a chemical mechanical polishing step is performed before depositing the mask layer.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform a polishing step on the second dielectric before depositing the mask layer in the method taught by the modified teachings of Mu ‘254 because performing a chemical mechanical polishing step on a layer forms substantially planar surfaces, as taught by Mu ‘254.
Claim(s) 13-14 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mu et al. ‘254 in view of Huang et al. ‘010 and Tran Quoc ‘220 as applied to claim 10 above, and further in view of Voronin et al. ‘018.
Claim 13: The modified teachings of Mu ‘254 teach the limitations of claim 10, as discussed above. With respect to claim 13, they do not explicitly teach that depositing the first dielectric layer comprises flowing a precursor gas mixture into a PECVD chamber through sidewall gas inlets at a first flow rate and a top gas inlet at a second rate, wherein the sidewall gas inlets are disposed on sidewalls of the PECVD chamber and the top gas inlet is disposed on a top plate of the PECVD chamber, applying a source power to form a plasma from the precursor gas mixture, and exposing the substrate to the plasma to deposit the first dielectric layer.
Voronin ‘018 teaches a method for manufacturing a semiconductor device (abstract, [0001]) comprising depositing a layer on a substrate ([0001]). Voronin ‘018 teaches that depositing the layer can comprise providing a plasma enhanced chemical vapor deposition chamber (Fig. 6, [0050]) comprising sidewall gas inlets (659) disposed on sidewalls of the PECVD chamber (Fig. 6, [0061]) and a top gas inlet (653) disposed on a top plate of the PECVD chamber (Fig. 6, [0060]), receiving the substrate (110) on a substrate holder (612) within the PECVD chamber (Fig. 6, [0051]), flowing a precursor gas into the PECVD chamber through the sidewall gas inlets at a first flow rate and the top gas inlet at a second flow rate (Fig. 6, [0060], [0061]), applying a source power to the top plate to form a plasma from the precursor gas ([0054]), and exposing the substrate to the plasma to deposit a layer over the substrate ([0026], [0050]). Both Voronin ‘018 and Mu ‘254 teach methods for manufacturing a semiconductor device (‘254, abstract; ‘018, abstract, [0001]) comprising depositing a layer on a substrate (‘254, abstract; ‘018, [0001]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the steps of providing a plasma enhanced chemical vapor deposition chamber comprising sidewall gas inlets disposed on sidewalls of the PECVD chamber and a top gas inlet disposed on a top plate of the PECVD chamber, receiving the substrate on a substrate holder within the PECVD chamber, flowing a precursor gas into the PECVD chamber through the sidewall gas inlets at a first flow rate and the top gas inlet at a second flow rate, applying a source power to the top plate to form a plasma from the precursor gas, and exposing the substrate to the plasma to deposit a layer over the substrate taught by Voronin ‘018 as the method of depositing the first dielectric layer in the method taught by the modified teaching of Mu ‘254 because it would have been a simple substitution that would have yielded predictable results.
Claim 14: With respect to claim 14, the modified teachings of Mu ‘254 do not explicitly teach that the first flow rate is faster than the second flow rate, or that a thickness ratio of the edge thickness to the center thickness is between 1.5:1 and 3.5:1.
Voronin ‘018 teaches a method for manufacturing a semiconductor device (abstract, [0001]) comprising depositing a layer on a substrate ([0001]). Voronin ‘010 teaches that the first flow rate through the sidewall gas inlets and the second flow rate through the top gas inlet are controlled to control plasma stability ([0002], [0042], [0060], [0061]). Both Voronin ‘018 and Mu ‘254 teach methods for manufacturing a semiconductor device (‘254, abstract; ‘018, abstract, [0001]) comprising depositing a layer on a substrate (‘254, abstract; ‘018, [0001]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the first and second flow rates, and, therefore, the first and second flow rates relative values, in the method taught by the modified teachings of Mu ‘254 because the first and second flow rates affect plasma stability, as taught by Voronin ‘010.
With respect to claim 14, the modified teachings of Mu ‘254 do not explicitly teach that a thickness ratio of the edge thickness to the center thickness is between 1.5:1 and 3.5:1.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a silicon nitride layer (abstract, [0057]). Huang ‘010 further teaches that the thickness profile, and therefore ratio of edge thickness to center thickness, affects the deposited layer’s ability to compensate asymmetric bowing the substrate ([0062]). Both Huang ‘010 and Mu ‘254 teach semiconductor device manufacturing methods (‘254, abstract; ‘010, abstract) comprising depositing a silicon nitride layer (‘254, abstract, col 5 ln 52-col 6 ln 7; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to optimize the ratio of the edge thickness to center thickness in the method taught by the modified teachings of Mu ‘254 because the thickness profile, and therefore ratio of edge thickness to center thickness, affects the deposited layer’s ability to compensate asymmetric bowing the substrate, as taught by Huang ‘010.
Claim 21: With respect to claim 21, the modified teachings of Mu ‘254 do not explicitly teach that the precursor gas comprises silane, ammonia, and nitrogen gas.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract, [0057]) where the deposited layer is silicon nitride ([0060]). Huang ‘010 teaches that the precursor for the silicon nitride can comprise silane, ammonia, and nitrogen gas ([0060]). Both Huang ‘010 and Mu ‘254 teach semiconductor device manufacturing methods (‘254, abstract; ‘010, abstract) comprising depositing a silicon nitride layer (‘254, abstract, col 5 ln 52-col 6 ln 7; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the precursor gas comprising silane, ammonia, and nitrogen gas taught by Huang ‘010 in the precursor gas in the modified teachings of Mu ‘254 because it is a suitable precursor gas for silicon nitride deposition, as taught by Huang ‘010.
Claim(s) 22-23 and 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Voronin et al. ‘018 in view of Hyeong et al. ‘033, Tran Quoc ‘220, and Huang et al. ‘010.
Claim 22: Voronin ‘018 teaches a method for processing a substrate (abstract, [0001]) comprising:
providing a plasma enhanced chemical vapor deposition chamber (Fig. 6, [0050]) comprising sidewall gas inlets (659) disposed on sidewalls of the PECVD chamber (Fig. 6, [0061]) and a top gas inlet (653) disposed on a top plate of the PECVD chamber (Fig. 6, [0060]);
receiving the substrate (110) on a substrate holder (612) within the PECVD chamber (Fig. 6, [0051]);
flowing a precursor gas into the PECVD chamber through the sidewall gas inlets at a first flow rate and the top gas inlet at a second flow rate (Fig. 6, [0060], [0061]);
applying a source power to the top plate to form a plasma from the precursor gas ([0054]); and
exposing the substrate to the plasma to deposit a layer over the substrate ([0026], [0050]).
Voronin ‘018 further teaches that the method is for semiconductor device manufacturing ([0001]).
With respect to claim 22, Voronin ‘018 does not explicitly teach that the layer is a dielectric, or that the top plate is a gas shower head comprising a plurality of concentric rings, each concentric ring comprising a plurality of gas nozzles, that flow rates through each concentric ring may be controlled such that the dielectric layer is deposited with a variable thickness, that the dielectric layer covers edges of the substrate, or that an edge thickness at the edges of the substrate is greater than a center thickness in a center region of the substrate.
Hyeong ‘033 teaches a semiconductor device manufacturing method ([0002]) comprising depositing a layer by plasma enhanced chemical vapor deposition ([0002]). Hyeong ‘033 teaches that the deposited film can be a silicon nitride film, which is a dielectric film ([0022]). Hyeong ‘033 teaches that the top plate of the deposition chamber can be a gas shower head (Fig. 3, [0002]) comprising an inner ring (210) and outer ring (230) which are concentric (Fig. 3, [0041]), where each ring comprises a plurality of gas nozzles (Fig. 3) and flow rate through each ring can be controlled to deposit a layer with varying thickness (Fig. 3, [0062]). Hyeong ‘033 teaches that this allows for control of thickness variation in the deposited film ([0062]). Both Hyeong ‘033 and Voronin ‘018 teach semiconductor device manufacturing methods (‘018, [0001]; ‘033, [0002]) comprising depositing a layer by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘033, [0002]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the silicon nitride film taught by Hyeong ‘033 as the deposited film in the method taught by Voronin ‘018 because it would have been a simple substitution that would have yielded predictable results.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the top plate comprising a gas shower head comprising an inner ring and outer ring which are concentric where each ring comprises a plurality of gas nozzles and flow rate through each ring can be controlled to deposit a layer with varying thickness taught by Hyeong ‘033 in the method taught by Voronin ‘018 because it allows for control of thickness variation in the deposited film, as taught by Hyeong ‘033.
With respect to claim 1, the modified teachings of Voronin ‘018 do not explicitly teach that the dielectric layer covers edges of the substrate, or that an edge thickness at the edges of the substrate is greater than a center thickness in a center region of the substrate.
Tran Quoc ‘220 teaches a semiconductor device manufacturing method ([0001]) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract) where the layer can be a dielectric layer (abstract). Tran Quoc ‘220 teaches that the dielectric layer can cover the edges of the substrate (Fig. 3, [0023], [0026], [0064]). Tran Quoc ‘220 teaches that this decreases the amount of etching radicals on the periphery of the substrate to allow substantially equal etching across the substrate surface ([0014], [0015]). Both Tran Quoc ‘220 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘220, [0001]) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘220, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the dielectric layer cover the edges of the substrate as taught by Tan Quoc ‘220 in the method taught by the modified teachings of Voronin ‘018 because this decreases the amount of etching radicals on the periphery of the substrate to allow substantially equal etching across the substrate surface, as taught by Tran Quoc ‘220.
With respect to claim 1, the modified teachings of Voronin ‘018 do not explicitly teach that an edge thickness at the edges of the substrate is greater than a center thickness in a center region of the substrate.
Huang ‘010 teaches a semiconductor device manufacturing method (abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (abstract, [0057]). Huang ‘010 teaches that the deposited layer can have an edge thickness that is larger than the center thickness ([0055], [0057]). Huang ‘010 teaches that this allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing (abstract, [0002], [0004], [0055]). Both Huang ‘010 and Voronin ‘018 teach semiconductor device manufacturing method (‘018, [0001]; ‘010, abstract) comprising depositing a layer on a substrate by plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘010, abstract, [0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the deposited layer have an edge thickness that is larger than the center thickness as taught by Huang ‘010 in the method taught by the modified teachings of Voronin ‘018 because it allows the deposited layer to compensate for stresses on the substrate to prevent asymmetric bowing during processing, as taught by Huang ‘010.
Claim 23: Voronin ‘018 teaches that the method can further comprise controlling a temperature of the substrate holder to maintain a substrate temperature during plasma deposition ([0052]).
Claim 25: Voronin ‘010 teaches that the method can comprise controlling the first flow rate through the sidewall gas inlets and the second flow rate through the top gas inlet during plasma processing ([0002], [0042], [0060], [0061]).
Claim 26: Voronin ‘010 teaches that the source power is applied using a power source ([0012]), the source power can be applied to a radial line slot antenna to form the plasma ([0020]), the top plate can comprise quartz ([0054]), and the power source can be microwave power comprising a microwave frequency ([0012]).
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Voronin et al. ‘018 in view of Hyeong et al. ‘033, Tran Quoc ‘220, and Huang et al. ‘010 as applied to claims 22-23 above, and further in view of Dhas et al. (U.S. Patent Application Publication 2021/0366705, hereafter Dhas ‘705).
The modified teachings of Voronin ‘018 teach the limitations of claims 22-23, as discussed above. Voronin ‘018 further teaches that the substrate holder can comprise a heater ([0052]) where the heater is a heating fluid flow ([0052]).
With respect to claim 24, the modified teachings of Voronin ‘018 do not explicitly teach that the heater is a resistive heater.
Dhas ‘705 teaches a method of manufacturing a semiconductor device ([0002]) comprising plasma enhanced chemical vapor deposition (abstract). Dhas ‘705 teaches that a resistive heater and heating fluid flow are functional equivalents for the purposes of being the heater in a substrate support ([0049]). Both Dhas ‘705 and Voronin ‘018 teach methods of manufacturing a semiconductor device (‘018, [0001]; ‘705, [0002]) comprising plasma enhanced chemical vapor deposition (‘018, Fig. 6, [0050]; ‘705, abstract).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the resistive heater taught by Dhas ‘705 for the heating fluid flow in the substrate support in the method taught by the modified teachings of Voronin ‘018 because a resistive heater and heating fluid flow are functional equivalents for the purposes of being the heater in a substrate support, as taught by Dhas ‘705.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BG/
/SHAMIM AHMED/ Primary Examiner, Art Unit 1713
