Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/17/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by “Patil” (US 2023/0086094).
Regarding claim 1, Patil anticipates 1. A semiconductor package, comprising: a dielectric layer (Fig. 1B, [0031]-[0032]; the uppermost insulating layer 114 is a dielectric layer);
a solder resist (SR) on the dielectric layer, the SR defining a first SR area, a second SR area, and a trench open area between the first SR area and the second SR area, wherein an upper surface of the dielectric layer is covered with the SR in the first SR area and the second SR area, and is not covered in the trench open area (Fig. 1B, [0031]-[0032]; the solder resist 120 is on the uppermost insulating layer 114, the solder resist 120 defining first and second areas and a trench at the metal traces 122 between the first and second areas, an upper surface of the uppermost insulating layer 114 is covered with the solder resist 120 in the first and second areas and not covered in the trench open area);
and one or more traces on the upper surface of the dielectric layer within the trench open area, wherein at least one trace of the one or more traces comprises an anchor on a lower surface thereof, the anchor penetrating the upper surface of the dielectric layer to a depth below the upper surface of the dielectric layer (Fig. 1B, [0031]-[0032]; the metal traces 122 are on the upper surface of the uppermost insulating layer 114 within the trench open area, and the embedded metal interconnect 116 and the via is an anchor penetrating the upper surface of the uppermost insulating layer 114 to a depth below the upper surface of the uppermost insulating layer 114).
Regarding claim 2, Patil anticipates 2. The semiconductor package of claim 1, wherein the semiconductor package comprises one or more dielectric layers stacked on each other, and wherein the dielectric layer is an outer dielectric layer of the one or more dielectric layers (Fig. 1B, [0031]-[0032]; the insulating layers 114 (1-3) are stacked on each other, and the uppermost insulating layer 114 is an outer dielectric layer on the stack).
Regarding claim 3, Patil anticipates 3. The semiconductor package of claim 2, wherein the semiconductor package comprises one or more metal layers formed on upper surfaces of corresponding one or more dielectric layers, and wherein the one or more traces are parts of a first metal layer formed on the upper surface of the dielectric layer (Fig. 1B, [0031]-[0032]; the embedded metal interconnects 116 (1-3) are metal layers formed on upper surfaces of corresponding one or more insulating layers 114 (1-3), and the metal traces 122 are are parts of a first metal layer formed on the upper surface of the insulating layer 114).
Regarding claim 4, Patil anticipates 4. The semiconductor package of claim 1, wherein the at least one trace and the anchor are integrally formed (Fig. 1B, [0031]-[0032]; the metal trace 122 and the embedded metal interconnect 116 and the via are integrally formed).
Regarding claim 8, Patil anticipates 8. The semiconductor package of claim 1, wherein a width of the anchor is less than or equal to half of a width of the trace (Fig. 1B, [0031]-[0032]; a width of the via is less than or equal to half of a width of the metal trace 122).
Regarding claim 9, Patil anticipates 9. The semiconductor package of claim 1, wherein the depth of penetration of the anchor into the dielectric layer is less than a height of the dielectric layer (Fig. 1B, [0031]-[0032]; a depth of penetration of the via into the uppermost insulating layer 114 is less than a height of the uppermost insulating layer 114).
Regarding claim 10, Patil anticipates 10. The semiconductor package of claim 1, wherein the anchor of the at least one trace is shaped as any one or more of a solid line, a dashed line, or a dotted line (Fig. 1B, [0031]-[0032]; the embedded metal interconnect 116 is shaped as a solid line),
the solid line comprising a single line along a first length portion of the at least one trace (Fig. 1B, [0031]-[0032]; the embedded metal interconnect 116 is a single line along a first length portion of the metal trace 122),
the dashed line comprising one or more dashes along a second length portion of the at least one trace, a length of a dash being greater than a width of the anchor, and the dotted line comprising one or more dots along a third length portion of the at least one trace, a length of a dot being less than or equal to the width of the anchor (Examiner’s note: Patil anticipates the limitation of claim 10 since the claim recites “a solid line, a dashed line, or a dotted line”.).
Regarding claim 11, Patil anticipates 11. The semiconductor package of claim 1, wherein the semiconductor package is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle ([0064]; Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, a drone, and a multicopter.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Patil in view of “Pun” (US 2020/0035594).
Regarding claim 5, Patil discloses the claimed invention as applied to claim 1, above.
Patil does not disclose the limitations of claim 5.
Pun discloses a width of the at least one trace is less than or equal to 8 μm (Fig. 6A, [0045]; a width of the at least one trace is about 4 μm).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Patil’s semiconductor package with Pun’s dimensions in order to optimize the semiconductor package for both diffusion bonding of chips and soldering of passives components, as suggested by Pun at Abstract.
Regarding claim 6, Patil discloses the claimed invention as applied to claim 1, above.
Patil does not disclose the limitations of claim 6.
Pun discloses a space between two adjacent traces of the one or more traces is less than or equal to 10 μm (Fig. 6A, [0045]; a space between two adjacent traces of the one or more traces is about 4 μm).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Patil’s semiconductor package with Pun’s dimensions in order to optimize the semiconductor package for both diffusion bonding of chips and soldering of passives components, as suggested by Pun at Abstract.
Regarding claim 7, Patil discloses the claimed invention as applied to claim 1, above.
Patil discloses 7. The semiconductor package of claim 1, wherein the semiconductor package further comprises: at least two contact structures in contact with corresponding at least two traces of the one or more traces, at least one contact structure comprising a bump and a bump pad (Figs. 1A, 1B, [0031]-[0032]; the IC die 108 comprises the interconnect bumps 126 that are connected to the metal interconnects 124).
Patil does not disclose a pitch between the at least two contact structures is less than or equal to 54 μm.
Pun discloses a pitch between the at least two contact structures is less than or equal to 54 μm (Fig. 6A, [0045]; a pitch between the at least two contact structures is between about 8 μm and 30 μm).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Patil’s semiconductor package with Pun’s dimensions in order to optimize the semiconductor package for both diffusion bonding of chips and soldering of passives components, as suggested by Pun at Abstract.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm.
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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