DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12, and 15 – 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0206187).
Regarding claim 12, Kim teaches (FIG. 1, 6, 8):
A semiconductor device comprising:
a substrate (“substrate”);
a first gate electrode (lower gate) on the substrate;
a first insulating layer (HZO) on the first gate electrode;
a first channel pattern (ITZO) and first and second source/drain electrodes on the first insulating layer;
a first interlayer insulating layer (“insulator” not shown) on the first channel pattern and the first and second source/drain electrodes;
a second gate electrode (upper gate) on the first interlayer insulating layer;
a second insulating layer (Al2O3) on the second gate electrode;
a second channel pattern (ITZO) and third and fourth source/drain electrodes on the second insulating layer; and
a storage node contact ([0065]) passing through the first interlayer insulating layer, and connecting the second source/drain electrode and the second gate electrode, wherein:
the first gate electrode and the second gate electrode vertically overlap each other;
the first source/drain electrode and the third source/drain electrode vertically overlap each other;
the second source/drain electrode and the fourth source/drain electrode vertically overlap each other; and
the first channel pattern and the second channel pattern vertically overlap each other (FIG. 6).
Regarding claim 15, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 12, wherein:
the first and second source/drain electrodes are spaced apart in a first direction parallel to the substrate; and
the third and fourth source/drain electrodes are spaced apart in the first direction.
Regarding claim 16, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 15, wherein the first and second source/drain electrodes are disposed on the first channel pattern and the first insulating layer.
Regarding claim 17, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 15, wherein the second channel pattern is disposed on the third and fourth source/drain electrodes and the second insulating layer.
Regarding claim 18, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 17, wherein the thickness of the second channel pattern is substantially uniform.
Regarding claim 19, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 15, wherein the third and fourth source/drain electrodes are disposed on the second channel pattern and the second insulating layer.
Regarding claim 20, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 12, further comprising a second interlayer insulating layer covering the third and fourth source/drain electrodes and the second channel pattern.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0206187) in view of Sato et al. (US 2023/0084611).
Regarding claim 1, Kim teaches (FIG. 1, 6, 8):
A semiconductor device comprising:
a substrate (FIG. 6, “substrate”);
a first transistor (lower transistor) on the substrate;
an interlayer insulating layer (“insulator” not shown) covering the first transistor;
a second transistor (upper transistor) on the interlayer insulating layer; and
a storage node ([0065]) contact passing through the interlayer insulating layer, and connecting any one of source/drain electrodes of the first transistor and a gate electrode of the second transistor.
Kim teaches varying performance based on semiconductor types of oxide semiconductor ([0070]), but fails to expressly disclose
a first channel pattern of the first transistor includes an n-type oxide transistor (); and
a second channel pattern of the second transistor includes an p-type oxide transistor.
However, Sato teaches vertically stacked two transistor capacitorless memory cell structures using oxide semiconductor channels wherein the oxide semiconductor channels may be formed selectively of either conductivity type depending on the desired performance and design characteristics ([0041] – [0056]).
It would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to form the channels of the individual stacked transistors of Kim of whichever conductivity type would provide the optimum performance for the desired final design, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See also Ballas Liquidating Co. v. Allied industries of Kansas, Inc. (DC Kans) 205 USPQ 331.
Regarding claim 2, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 1, wherein the first channel pattern and the second channel pattern vertically overlap each other.
Regarding claim 3, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 1, wherein the first transistor comprises a first gate electrode on the substrate, a first insulating layer on the first gate electrode, the first channel pattern on the first insulating layer, and first and second source/drain electrodes, wherein the first and second source/drain electrodes are spaced apart in a first direction parallel to the substrate.
Regarding claim 4, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 1, wherein the second transistor comprises a second gate electrode on the interlayer insulating layer, a second insulating layer on the second gate electrode, the second channel pattern on the second insulating layer, and third and fourth source/drain electrodes, wherein the third and fourth source/drain electrodes are spaced apart in the first direction.
Regarding claim 5, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 1, wherein the first gate electrode of the first transistor and the second gate electrode of the second transistor extend in a second direction parallel to the substrate and vertically crossing the first direction.
Regarding claim 6, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 2, wherein the first and second source/drain electrodes are disposed on the first channel pattern and the first insulating layer.
Regarding claim 7, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 3, wherein the second channel pattern is disposed on the third and fourth source/drain electrodes and the second insulating layer.
Regarding claim 8, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 7, wherein the thickness of the second channel pattern is substantially uniform.
Regarding claim 9, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 3, wherein the third and fourth source/drain electrodes are disposed on the second channel pattern and the second insulating layer.
Regarding claim 10, Kim teaches (FIG. 1, 6, 8):
The semiconductor device of claim 1, wherein the storage node contact vertically overlaps the first channel pattern and the second channel pattern.
Regarding claim 11, Kim fails to expressly disclose:
The semiconductor device of claim 1, wherein the second channel pattern comprises a chalcogenide material.
However, Sato teaches various channel layers which include recognized chalcogenide memory materials such as selenium or tellurium ([0041]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a chalcogenide material as taught by Sato in the channel of Kim, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See also Ballas Liquidating Co. v. Allied industries of Kansas, Inc. (DC Kans) 205 USPQ 331.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0206187) as applied to claim 12 above, and further in view of Sato et al. (US 2023/0084611).
Regarding claim 13, Kim teaches varying performance based on semiconductor types of oxide semiconductor ([0070]), but fails to expressly disclose:
The semiconductor device of claim 12, wherein: the first channel pattern comprises an n-type oxide transistor; and the second channel pattern comprises a p-type oxide transistor.
However, Sato teaches vertically stacked two transistor capacitorless memory cell structures using oxide semiconductor channels wherein the oxide semiconductor channels may be formed selectively of either conductivity type depending on the desired performance and design characteristics ([0041] – [0056]).
It would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to form the channels of the individual stacked transistors of Kim of whichever conductivity type would provide the optimum performance for the desired final design, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See also Ballas Liquidating Co. v. Allied industries of Kansas, Inc. (DC Kans) 205 USPQ 331.
Regarding claim 14, Kim fails to expressly disclose:
The semiconductor device of claim 13, wherein the second channel pattern comprises a chalcogenide material.
However, Sato teaches various channel layers which include recognized chalcogenide memory materials such as selenium or tellurium ([0041]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a chalcogenide material as taught by Sato in the channel of Kim, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. See also Ballas Liquidating Co. v. Allied industries of Kansas, Inc. (DC Kans) 205 USPQ 331.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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