DETAILED ACTION
This action is responsive to the following communications: the Application filed on September 20, 2024 and the Foreign Priority papers retrieved on April 30, 2024.
Claims 1-20 are pending. Claims 1, 16 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukushima et al. (US 5654913).
With respect to independent claim 1, Fukushima et al. disclose a memory [see Fig. 1], comprising:
a plurality of word lines [Fig. 1: WL, col. 5, lines 55-56];
a plurality of memory cells coupled with each word line [see Fig. 1, the memory cell 22 includes an NMOS memory cell transistor 4 that is connected to the word line WL, col. 5, lines 53-54 as well as lines 66-67] and
a peripheral circuit [Fig. 1: 6] coupled to the plurality of word lines [a reference numeral 6 denotes a word driver circuit for driving the word line WL, col. 5, lines 56-57] and configured to:
during a refresh operation on a memory cell coupled with at least one selected word line in the plurality of word lines, apply a first voltage to an unselected word line adjacent to the selected word line [see Fig. 4, during the refresh period, the unselected word lines WL are supplied with the predetermined potential VWL1 (=0 V) by the word driver circuit 6, col. 8, lines 54-56] by turning on a first voltage transmission circuit and at least partially turning off a second voltage transmission circuit [see Fig. 4, when the word line WL belonging thereto is not selected during the operation and in the refresh period in the standby state, the first transistor Q7 is turned on in the word line potential switching circuit 10, thereby supplying the normal potential VWL1 (=Vss) to the ground line Eth of the word driver circuit 6 while the second transistor Q6 is turned off in the word line potential switching circuit 10, col. 8, lines 1-6].
With respect to independent claim 17, Fukushima et al. disclose an operation method of a memory, comprising:
during a refresh operation on a memory cell coupled with at least one selected word line in a plurality of word lines, applying a first voltage to an unselected word line adjacent to the selected word line [see Fig. 4, during the refresh period, the unselected word lines WL are supplied with the predetermined potential VWL1 (=0 V) by the word driver circuit 6, col. 8, lines 54-56] by turning on a first voltage transmission circuit and at least partially turning off a second voltage transmission circuit [see Fig. 4, when the word line WL belonging thereto is not selected during the operation and in the refresh period in the standby state, the first transistor Q7 is turned on in the word line potential switching circuit 10, thereby supplying the normal potential VWL1 (=Vss) to the ground line Eth of the word driver circuit 6 while the second transistor Q6 is turned off in the word line potential switching circuit 10, col. 8, lines 1-6].
Allowable Subject Matter
Claims 2-15 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 2, the applied prior art, Fukushima et al. (US 5654913) shows a word line driver circuit that has a “first voltage transmission circuit” (Fig. 4: Q7, which applies VSS or 0V) and a “second voltage transmission circuit” (Fig. 4: Q8, which applies VBB or -1.5V as an example). Fukushima et al. disclose refresh operations for the DRAM but do not mention the read or write operations because the Fukushima et al. patent is directed to extending data retention times (see Title). However, Fukushima et., by disclosing a DRAM, would be understood as having the read and write functionality required by a memory (i.e., storage and retrieval function is required). As would also have been understood in the DRAM, a DRAM cell selected for operation (either read or write) must activate its access transistor by activating the access transistor’s gate by the word line such that data can be read out or written in by its bit line from or to its storage capacitor. DRAM cells that are not to be disturbed during a read or write operation must have their access transistor deactivated, by applying a logic low (i.e., VSS) to the access transistor’s gate by the word line. Fukushima et al. show their DRAM cell’s access transistor is a NFET (Fig. 1: 4). NFETs are activated by applying logic high (i.e., VDD) to its word line and deactivated by applying logic low (i.e., VSS) to its word line.
By disclosing the NFET access transistor (Fg. 1: 4), which for unselected memory cells must be deactivated by logic low (i.e., VSS), Fukushima et al. impliedly disclose the peripheral circuit (Fig. 1: 6; see Fig. 4) is further configured to: during a read or write operation on a memory cell coupled with one selected word line in the plurality of word lines (read or write operations to memory cells on a selected word line is required operations for all DRAM), apply the first voltage (i.e. VSS) to the unselected word line adjacent to the selected word line by turning on the first voltage transmission circuit (Fig. 4: Q7).
However dependent claim 2 requires not just activating the “first voltage transmission circuit” but also activating the “second voltage transmission circuit” to generate the voltage to apply to the unselected word line. Here, Fukushima et al. would not be expected to activate their “second voltage transmission circuit” (Fig. 4: Q6), supplying -1.5V, to generate a unselected word line voltage.
For this reason, Fukushima do not teach or suggest during a read or write operation on a memory cell coupled with one selected word line in the plurality of word lines, apply the first voltage to the unselected word line adjacent to the selected word line by turning on the first voltage transmission circuit and turning on the second voltage transmission circuit.
With respect to claim 18, similar to the reasons for claim 2, the applied prior art, Fukushima et al. (US 5654913), do not teach or suggest during a read or write operation on a memory cell coupled with one selected word line in the plurality of word lines, applying the first voltage to the unselected word line adjacent to the selected word line by turning on the first voltage transmission circuit and turning on the second voltage transmission circuit.
Thus, there is no teaching or suggestion in the prior art of record to provide the recited during a read or write operation on a memory cell coupled with one selected word line in the plurality of word lines, applying the first voltage to the unselected word line adjacent to the selected word line by turning on the first voltage transmission circuit and turning on the second voltage transmission circuit.
Claim 16 is allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to independent claim 16, there is no teaching or suggestion in the prior art of record to provide the recited a peripheral circuit coupled to the plurality of word lines, the peripheral circuit comprising a first voltage generator, a second voltage generator, a first voltage transmission circuit, a second voltage transmission circuit, a third voltage transmission circuit, and a plurality of word-line driver circuits, wherein the first voltage transmission circuit and the second voltage transmission circuit are connected in parallel between the first voltage generator and the plurality of word-line driver circuits, the third voltage transmission circuit is connected between the second voltage generator and the plurality of word-line driver circuits, and the plurality of word-line driver circuits are coupled with the plurality of word lines, in combination with others limitations.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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