DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15, in the reply filed on 8/3/2026 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hutchison et al (US 2008/0280099).
Regarding claim 1, Hutchison et al disclose a process of making an window for electron transmission, wherein the process comprising the steps of providing a base wafer 200; forming a first thin film (202) on a front side of the wafer and a second thin film (203) on an opposite side of the wafer; After photolithographic patterning, openings such as the representative opening 208 are formed in the photoresist layer 204. The substrate and patterned photoresist are exposed to an etch suitable for removing thermal oxide, and openings such as the representative opening 210 are formed in the thermal oxide layer 202 so that a patterned thermal oxide layer is formed. The patterned thermal oxide is then used to define exposed portions of the silicon substrate that can be etched with an etch process that does not etch thermal oxide (or slowly etches thermal oxide) so that thermal oxide windows (such as the representative window 212) are formed in the thermal oxide layer 203, where trenches are formed by removing the bulk core wafer by wet etching using TMAH and such trenches appears to sectioning of the base wafer ([0038]; Figure 2).
Hutchison et al disclose that the TEM grid 905 is shown enlarged in FIG. 9b. The substrate 900 is typically a silicon substrate, and the TEM grids 902-910 are separated from the substrate 900 with respective channels 922-930. For silicon substrates, the channels 922-930 can be defined by etching the substrate. For example, the channels can be defined by etching a silicon substrate down to an oxide layer in a manner similar to that used to define the TEM grids as described above so that perimeters of the TEM grids 902-910 are attached to the substrate 900 by an oxide layer and/or one or more tabs. Alternatively, the channels can be completely etched through the silicon substrate and the oxide layer, ZZ leaving the TEM grids 902-910 attached to the substrate 900 only at the tabs [0057].
Regarding claim 2, Hutchison et al disclose that thinning the window by dry etching, after wet-etching [0056].
Claim(s) 1-3, 5-6,10-13 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ohara et al (US 2017/0324063).
Regarding claim 1, Ohara et al disclose a method for preparing electron transparent substrate (a method for producing a light-emitting element; ([0001]), the method comprising: providing a base wafer having a bulk core (a substrate formed with thin film transistors as active elements; [00641]), a first thin film layer disposed on one side of the bulk core corresponding with a frontside of the base wafer (an electroluminescence layer including at least a light emitting layer is disposed on a first side of the substrate; (Fig.1B, [0035]), and a second thin film layer disposed on an opposite side of the bulk core corresponding with a backside of the base wafer (an interlayer insulating layer on the substrate is disposed on a back side of the substrate; Fig. 1B, [0035]); subjecting the base wafer, on the backside, to (i) photolithography to define removal regions (a method for patterning the surface of the interlayer insulating layer 31 by using a photolithographic method; [0141], and to (ii) etching to remove portions of the second thin film layer corresponding to the defined removal regions to allow exposure of bulk core via the backside of the base wafer (a contact hole 32 is formed in the interlayer insulating layer 31 by etching the interlayer insulating layer 31 above the drive TFT (thin film transistor) 23a using the developed photosensitive resist 61 as a mask; as a result, the drive TFT 23a is exposed; [0205]); and subjecting the base wafer, on the backside, to wet etching to remove portions of the bulk core (a first trench portion is formed (portions of the base are removed) in the interlayer insulating layer 31 by half etching (which may be wet etching) the interlayer insulating layer 31; [0208], wherein removed portions of the bulk core include thickened portions of the bulk core extending through the bulk core to the first thin film layer to expose portions of the first thin film layer via the backside to define electron transport windows (the electroluminescent layer 42 may include layers such as a hole injecting layer, a hole transport layer, an electron transport layer, and an electron injecting layer, thereby forming an electron transparent ''window"; [0186], and trench portions extending partially into the bulk core from the backside to define trenches for sectioning of the base wafer (forming at least one trench including a concave-convex portion of submicron order in a region for forming a light-emitting region of an interlayer insulating layer layered on a substrate [0039].
Regarding claim 2, Ohara et al disclose above the method of claim 1, further comprising subjecting the base wafer to dry etching for thickness reduction of the first thin film layer (the EL layer 42, and the second electrode 43 are formed so as to have a thickness of each layer greater than or equal to the concave-convex height of the concave-convex portion in the lower layers with which each of the first electrode 41, the EL layer 42, and the second electrode 43 contacts, and have a uniform thickness; these components may be formed by using an etching method on a film on the EL layer ([0159], [0176]).
Regarding claim 3, Ohara et al disclose above the method of claim 2, wherein subjecting the base wafer to dry etching for thickness reduction of the first thin film layer comprises thickness reduction of the first thin film layer in regions including the electron transparent windows (adjusting the thickness of the EL layer, which comprises the hole transport layers, electron transport layers, and electron injecting layers (together, the window) adjusts the thickness of the electron transparent windows; [0159], [0176], [0186]).
Regarding claim 5, Ohara et al disclose above for claim 1, wherein subjecting the base wafer to wet etching to remove trench portions comprises partially removing portions of the bulk core as the trench portions such that the defined trenches do not extend entirely through the bulk core to the first thin film layer (in the interlayer insulating layer 31, at a position corresponding to the light-emitting region 13 of the respective sub pixel circuit portions 12, a trench having a step shape is formed from a plurality of trench portions each having an indented shape serving as a plurality of walls and banks [0124].
Regarding claim 6, Ohara et al disclose above for the method of claim 5, further comprising cleaving the wafer into samples according to sectioning as defined by the trenches (the trenches separate the wafer into various regions based on the trench portions associated with each region [0127].
Regarding claim 10, Ohara et al disclose above the method of claim 1, further comprising modifying the base wafer (applying an interlayer insulating layer 31 to the substrate [0035]).
Regarding claim 11, Ohara et al disclose above the method of claim 10, wherein modifying the base wafer includes one or more of atomic layer deposition of thin films, chemical vapor deposition of surface modifiers, spin-coating with polymeric or thin films (the interlayer insulating layer is applied via chemical vapor deposition, sputtering, or spin-coating [0130].
Regarding claim 12, Ohara et al disclose above the method of claim 11, wherein modifying the base wafer includes depositing conductive material near substrate edges (forming the electrode on the base wafer includes forming an electrode of a conductive material [0167].
Regarding claim 13, Ohara et al disclose above the method of claim 11, wherein modifying is performed before subjecting the base wafer, on the backside, to photolithography (forming a thin film of the electrode materials stated above using a method such as vapor deposition or sputtering, and then using a known method such as photolithography (the electrodes are patterned using photolithography) [0167].
Regarding claim 15, Ohara et al disclose above the method of claim 1, further comprising frontside processing (processing the front side to form the EL layer and first and second electrodes [0176].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohara et al (US 2017/0324063).
Regarding claim 4, Ohara et al disclose above the method of claim 2.
Ohara et al fails to disclose wherein subjecting the base wafer to dry etching comprises reactive plasma etching.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use plasma etching because it is well known technique in the art of semiconductor manufacturing as a process to develop patterns on silicon wafers for microelectronic devices.
Regarding claim 14, Ohara et al disclose above the method of claim 11.
Ohara et al fails to disclose wherein modifying is performed after subjecting the base wafer, on the backside, to photolithography, and before subjecting the base wafer, on the backside, to wet etching.
However, Ohara et al disclose that subjecting the wafer to photolithography ([0176]) and wet etching the wafer ([0205]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ohara et al such that the processes take place in the specified order because the order of the processes may be modified for different desired configurations of the substrate assembly.
Allowable Subject Matter
Claims 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or renders obvious to a process, including the step of sectioning includes sample sectioning the base wafer into sample sections and sub-sectioning the sample sections into sub-sample sections, and cleaving includes cleaving the base wafer into samples according to the sample sections and sub- cleaving the samples into sub-samples according to the sub-sample sections as the context of claim 7.
Claims 8-9 are directly or indirectly depending on the claim 7 and therefore, also allowable.
Conclusion
The prior art made of record, listed in the PTO-892 and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAMIM AHMED whose telephone number is (571)272-1457. The examiner can normally be reached M-TH (8-5:30pm).
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SHAMIM AHMED
Primary Examiner
Art Unit 1713
/SHAMIM AHMED/ Primary Examiner, Art Unit 1713
