DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted has been considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-9, 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2014/0211563 “Chang”) in view of Dunga et al. (US 2014/0254269 “Dunga”).
Regarding claim 1, Chang discloses a memory device, comprising:
a memory cell array (212; fig. 17) including vertically stacked memory cells (“vertical word lines between the stacks with memory cells at cross points between the vertical word lines” [0013]); and
a controller (234; fig. 17) configured to:
program first memory cells (memory cells of a selected string for program, i.e. the selected string comprising memory cell 26; fig. 1) of the vertically stacked memory cells based on a first program method (hot-carrier injection [0045]) and a second program method (FN programming [0045]) (“Va gives local boosting between WL(n) 16 to GSL(even) 12 and causes additional hot-carrier injection into selected memory cell 26, until WL(n+1) 17 is turned on with Vpass. After WL(n+1) 17 is turned on, conventional +FN programming is performed, into selected memory cell 26” [0045], i.e. memory cell 26 is program using first and second program method [0054-0056]), and
wherein a first voltage (Vpass, Vpass2; fig. 5) applied to a first unselected memory cell adjacent (any first memory cell coupled to an unselected word line that is adjacent to selected word line WL(n); fig. 5) to a first selected memory cell (26) among the first memory cells in a first program operation (i.e. hot-carrier programming [0061]) based on the first program method (i.e. hot-carrier injection) is different from a second voltage (Va; fig. 6) applied to a second unselected memory cell adjacent (any second memory cell coupled to another unselected word line, i.e. WL(n+1), that is adjacent to selected word line WL(n); fig. 6) to selected memory cell (26) among the first memory cells based on the second program method (i.e. FN programming).
Chang does not expressly disclose program second memory cells of the vertically stacked memory cells based on the first program method, a second selected memory cell among the first memory cells in a second program operation.
Dunga discloses program (in one program cycle of M program cycles [0060]) second memory cells (any second memory cell of another selected block of memory cells; fig. 9-12 [0061]) of the vertically stacked memory cells (i.e. three dimensional array of memory cells [0054]) based on the first program method (fig. 15A-15D), a second selected memory cell (any second selected memory cell of a selected block of memory cells; fig. 9-12) among the first memory cells (i.e. memory cells of the selected block of memory cells) in a second program operation (i.e. any second program after a first program; fig. 9-12).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dunga is modifiable as taught by Chang for the purpose of allowing selective programming of the device while achieving optimal threshold voltage levels [Abstract of Dunga]), which is consistent with program sequences respective of unselected memory cells adjacent to selected memory cells, as common and well known in the prior art to secure the integrity of data storage.
Regarding claim 4, Chang discloses the memory device of claim 1, wherein the first memory cells are stacked above the second memory cells (fig. 1 [0013]).
Regarding claim 5, Chang discloses the memory device of claim 1, wherein the second voltage is lower than the first voltage (fig. 5, 6).
Regarding claim 6, Chang discloses the memory device of claim 1, wherein the second voltage is applied to the second unselected memory cell to separate a channel of a selected cell string including the second selected memory cell and the second unselected memory cell [0046].
Regarding claim 7, Chang discloses the memory device of claim 6, wherein the second voltage (Va; fig. 6) is lower than a third voltage (Vpass; fig. 5) applied to third unselected memory cells not adjacent (any third memory cell coupled to another unselected word line, i.e. other WL; fig. 5) to the second selected memory cell (i.e. of WL(n+1)) included in the selected cell string.
Regarding claim 8, Chang discloses the memory device of claim 6, wherein a level of the second voltage is close to a ground voltage (fig. 4-7).
Regarding claim 9, Chang discloses the memory device of claim 6, wherein the second voltage is a negative voltage [0062].
Regarding claim 12, Chang discloses the memory device of claim 1, wherein the controller is further configured to perform for the first memory cells, wherein a first program is performed by the first program method, and wherein a second program after the first program is performed by the second program method [0054-0056].
Chang does not expressly disclose a plurality of first program loops, wherein a first program loop of the plurality of first program loops is performed by program method, and wherein a second program loop after the first program loop is performed by the program method.
Dunga discloses a plurality of first program loops, wherein a first program loop of the plurality of first program loops is performed by program method, and wherein a second program loop after the first program loop is performed by the program method (i.e. in loops of M program cycles [0060]).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dunga is modifiable as taught by Chang for the purpose of allowing selective programming of the device while achieving optimal threshold voltage levels [Abstract of Dunga]), which is consistent with program sequences respective of unselected memory cells adjacent to selected memory cells, as common and well known in the prior art to secure the integrity of data storage.
Regarding claim 13, Chang does not expressly disclose the memory device of claim 12, wherein the first program loop and the second program loop are classified based on a reference program loop.
Dunga discloses wherein the first program loop and the second program loop are classified based on a reference program loop (i.e. programming dummy select gates; para 0059).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dunga is modifiable as taught by Chang for the purpose of allowing selective programming of the device while achieving optimal threshold voltage levels [Abstract of Dunga]), which is consistent with program sequences respective of unselected memory cells adjacent to selected memory cells, as common and well known in the prior art to secure the integrity of data storage.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2014/0211563 “Chang”) in view of Dunga et al. (US 2014/0254269 “Dunga”), further in view of Chen et al. (US 2010/0172188 “Chen”).
Regarding claim 2, Chang discloses the memory device of claim 1, wherein the program method is a method of F-N tunneling program operation, and wherein the program method is a method of hot carrier injection (HCI) program operation [0054-0056].
Chang as modified does not expressly disclose the first method is F-N tunneling program operation, and wherein the second method is hot carrier injection (HCI) program operation.
Chen discloses the first method is F-N tunneling program operation, and wherein the second method is hot carrier injection (HCI) program operation (FN tunneling is first method at S503, followed by second method HCI program at S506; fig. 5).
Hot carrier injection (HCI) and Fowler-Nordheim (F-N) tunneling are common and well known programming methods. Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chang is further modifiable as taught by Chen for the purpose of maintaining optimal threshold distributions of memory cells to prevent disturbances such as leakage ([0021-0022] of Chen), which is consistent with known practices in the prior art for improving the integrity of data storage.
Claim(s) 3, 10, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2014/0211563 “Chang”) in view of Dunga et al. (US 2014/0254269 “Dunga”), and further in view of Choe et al. (US 2012/0195125 “Choe”).
Regarding claim 3, Chang as modified does not expressly disclose memory device of claim 1, wherein first diameters of channel holes corresponding to the first memory cells are larger than second diameters of channel holes corresponding to the second memory cells.
Choe discloses a first diameter of a channel hole corresponding to the first memory cell (a diameter of channel hole 114 of pillar PL that is coupled to a memory cell of a top word line WL; fig. 3, 4, 7) are larger than a second diameter of a channel hole corresponding to the second memory cell (a diameter of channel hole 114 of pillar PL that is coupled to a memory cell of a bottom word line WL; fig. 3, 4, 7) (a diameter of a channel hole is larger at the top of memory stack than a diameter of a channel hole at the bottom; fig. 3, 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chang is further modifiable
as taught by Choe for the purpose of facilitating data accessing schemes by allowing different
memory cells to be accessed independently from each other ([0254] of Choe), which is common and well known in the art to provide more flexibility in a given set of design parameters or performance constraints.
Regarding claim 10, Chang as modified does not expressly disclose memory device of claim 1, wherein the first and second selected memory cells are classified based on a reference word line.
Choe discloses the first and second selected memory cell are classified based on a reference word line (i.e. above or below any of a reference word line DMC2, DMC1; fig. 33).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chang is further modifiable as taught by Choe for the purpose of facilitating data accessing schemes by allowing different memory cells to be accessed independently from each other ([0254] of Choe), which is common and well known in the art to provide more flexibility in a given set of design
parameters or performance constraints.
Regarding claim 15, Chang discloses a memory device, comprising:
a memory cell array (212; fig. 17) including vertically stacked memory cells (“vertical word lines between the stacks with memory cells at cross points between the vertical word lines” [0013]); and
a controller configured to:
program first memory cells (memory cells of a selected string for program, i.e. the selected string comprising memory cell 26; fig. 1) of the vertically stacked memory cells based on a method of F-N tunneling program operation and a method of a HCI program operation (“Va gives local boosting between WL(n) 16 to GSL(even) 12 and causes additional hot-carrier injection into selected memory cell 26, until WL(n+1) 17 is turned on with Vpass. After WL(n+1) 17 is turned on, conventional +FN programming is performed, into selected memory cell 26” [0045, 0054-0056]).
Chang does not expressly disclose program second memory cells of the vertically stacked memory cells based on the method of F-N tunneling program operation, wherein first diameters of channel holes corresponding to the first memory cells are larger than second diameters of channel holes corresponding to the second memory cells.
Dung discloses program (in one program cycle of M program cycles [0060]) second memory cells (any second memory cell of another selected block of memory cells; fig. 9-12 [0061]) of the vertically stacked memory cells (i.e. three dimensional array of memory cells [0054]) based on the method of F-N tunneling program operation (fig. 15A-15D).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Dunga is modifiable as taught by Chang for the purpose of allowing selective programming of the device while achieving optimal threshold voltage levels [Abstract of Dunga]), which is consistent with program sequences respective of unselected memory cells adjacent to selected memory cells, as common and well known in the prior art to secure the integrity of data storage.
Choe discloses a first diameter of a channel hole corresponding to the first memory cell (a diameter of channel hole 114 of pillar PL that is coupled to a memory cell of a top word line WL; fig. 3, 4, 7) are larger than a second diameter of a channel hole corresponding to the second memory cell (a diameter of channel hole 114 of pillar PL that is coupled to a memory cell of a bottom word line WL; fig. 3, 4, 7) (a diameter of a channel hole is larger at the top of memory stack than a diameter of a channel hole at the bottom; fig. 3, 4).
Therefore, it would have been obvious to one with ordinary skill in the art before the effective filing date of the invention to recognize that the device of Chang is further modifiable as taught by Choe for the purpose of facilitating data accessing schemes by allowing different memory cells to be accessed independently from each other ([0254] of Choe), which is common and well known in the art to provide more flexibility in a given set of design parameters or performance constraints.
Regarding claim 16, Chang discloses the memory device of claim 15, wherein the first memory cells are disposed above the second memory cells (fig. 1 [0013]).
Regarding claim 17, Chang discloses the memory device of claim 15, wherein the memory device is configured such that the controller, when performing a program according to the method of the HCI program operation for a selected memory cell among the first memory cells (fig. 4-7), controls a switching voltage to be applied to a switching memory cell adjacent to (any memory cell coupled to another word line, i.e. WL(n+1), that is adjacent to selected word line WL(n); fig. 6) the selected memory cell (26; fig. 1) to separate a channel of a selected cell string including the selected memory cell and the switching memory cell [0046].
Regarding claim 18, Chang discloses the memory device of claim 17, wherein the switching voltage (Va; fig. 6) is lower than a pass voltage (Vpass; fig. 5) applied to unselected memory cells included in the selected cell string (any other unselected memory cells coupled to another unselected word line, i.e. other WL; fig. 5).
Regarding claim 19, Chang discloses the memory device of claim 17, wherein a level of the switching voltage is close to a ground voltage (fig. 4-7).
Regarding claim 20, Chang discloses the memory device of claim 17, wherein the switching voltage has a negative level [0062].
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (US 2014/0211563 “Chang”) in view of Dunga et al. (US 2014/0254269 “Dunga”), and further in view of Kim et al. (US 2008/0025106, hereinafter Kim).
Regarding claim 11, Chang as modified does not expressly disclose the memory device of claim 1, wherein the first and second selected memory cells are classified based on information about a program speed of the vertically stacked memory cells.
Kim discloses wherein a first program operation speed is slower (i.e. using hot channel
Injection [0006]) than a second program operation speed (i.e. using F-N tunneling [0050]).
Therefore, it would have been obvious to one with ordinary skill in the art before the
effective filing date of the invention to recognize that the device of Chang is further modifiable
as taught by Kim, wherein the second selected memory cell programmed with F-N tunneling is
faster than a program speed of the first selected memory cell programmed with hot channel
injection, for the purpose of facilitating data accessing schemes by improving the overall
performance speed ([0050] of Kim).
Allowable Subject Matter
Claim(s) 14 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations.
With respect to dependent claim , the prior art fails to teach or suggest the claimed limitations, namely wherein a level of a first program voltage used in the first program loop is higher than a level of a reference voltage, and wherein a level of a second program voltage used in the second program loop is lower than the level of the reference voltage.
The allowable claims are supported in at least fig. 23 of the instant application.
Conclusion
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/UYEN SMET/
[AltContent: connector] Primary Examiner, Art Unit 2824
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