DETAILED ACTION
Claim Objections
Claim 20 is objected to because of the following informalities:
Claim 20 recites “the side sector” which is first introduced in claim 12. As such claim 20 should be dependent on claim 12 instead of claim 11.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 10 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tomita (US 20010002179 A1)
Regarding claim 1, Tomita discloses A semiconductor package (40, Fig. 1), comprising: a carrier substrate (board, ¶ [0054]) comprising a first surface and a second surface opposite to the first surface; a first electronic component (10) and a second electronic component (20) mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the first electronic component is provided with a plurality of first data (DQ) pads (31) along a first side directly facing the second electronic component, wherein the second electronic component is provided with a plurality of second data (DQ) pads (35) along a second side in proximity to the first electronic component; and a plurality of first bond wires (44) directly connecting the plurality of first DQ pads to the plurality of second DQ pads.
Regarding claim 10, Tomita discloses the semiconductor package according to claim 1, wherein the second electronic component is a memory chip (DRAM 20).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6, 9 is/are rejected under 35 U.S.C. 103 as being unpatentable by Tomita (US 20010002179 A1) in view of Akamatsu (US 5983331 A)
Regarding claim 2, Tomita discloses the semiconductor package according to claim 1. Tomita is silent regarding wherein the first electronic component is further provided with a plurality of first command/address (CA) pads along the first side directly facing the second electronic component, and the second electronic component is further provided with a plurality of second command/address (CA) pads along the second side directly facing the first electronic component, wherein the plurality of first CA pads is directly and electrically connected to the second CA pads through a plurality of second bond wires.
Akamatsu discloses (Fig. 2, col. 3, lines 40-49) a mother chip connecting to a subsidiary chip using a face-to-face terminal block that comprises data terminals (16a/26a for mother chip/subsidiary chip respectively) and control signals (16f/26f for mother chip/subsidiary chip respectively). Akamatsu asserts the face-to-face packaging allows for the narrow pitch of the bonding terminals and such increasing terminal density.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add control signals bonding terminals as taught by Akamatsu into the package design of Tomita, along with the data pads, to increase effective communication bandwidth of the package.
Regarding claim 3, Tomita in view of Akamatsu discloses the semiconductor package according to claim 2. Tomita further discloses (Fig. 1, ¶ [0053]) wherein the first electronic component is further provided with a plurality of first power/ground pads (Vcc, Vss) in an elongated sector in front of the plurality of first DQ pads and the plurality of first CA pads along the first side (the modified package of Tomita-Akamatsu including the adding of CA pads to the pads of Tomita).
Regarding claim 4, Tomita in view of Akamatsu discloses the semiconductor package according to claim 3. Tomita further discloses (Fig. 1) wherein the plurality of first power/ground pads is directly and electrically connected to a plurality of first gold fingers (inner lead 42 denoting Vcc, Vss on the center top of of package 40, Tomita does not disclose “gold inner lead 42”) on the first surface of the carrier substrate through a plurality of third bond wires (bond wires connecting Vcc, Vss of logic chip 10 to inner leads 42).
While Tomita does not disclose inner leads (42) as gold fingers, Tomita discloses the lead lines 44 connecting data signals between the first and second chips as gold. Artisans in the art would have appreciated that gold fingers can be used to make reliable connections in a lead frame because they can provide low contact resistance and corrosion protection, as such it would have been obvious to one of ordinary skill in the art before the filing date of the invention to select gold (e.g. gold alloy plating) as the connector material of the fingers as taught by Tomita. Doing so would allow for remarkable resistance to corrosion and outstanding conductivity.
Regarding claim 5, Tomita in view of Akamatsu discloses the semiconductor package according to claim 4. Tomita further discloses (Fig. 1, ¶ [0053]) wherein the second electronic component (20) is further provided with a plurality of second power/ground pads (Vcc, Vss) between the second DQ pads and the first CA pads (the modified package of Tomita-Akamatsu including the adding of CA pads to the pads of Tomita).
Regarding claim 6, Tomita in view of Akamatsu discloses the semiconductor package according to claim 5. Tomita further discloses (Fig. 1) wherein the plurality of second power/ground pads (Vcc, Vss) is directly and electrically connected to a plurality of second gold fingers (inner lead 42 denoting Vcc, Vss on the center top of of package 40, Tomita does not disclose “gold inner lead 42”) on the first surface of the carrier substrate through a plurality of fourth bond wires (bond wires connecting Vcc, Vss of memory chip 20 to inner leads 42).
While Tomita does not disclose inner leads (42) as gold fingers, Tomita discloses the lead lines 44 connecting data signals between the first and second chips as gold. Artisans in the art would have appreciated that gold fingers can be used to make reliable connections in a lead frame because they can provide low contact resistance and corrosion protection, as such it would have been obvious to one of ordinary skill in the art before the filing date of the invention to select gold (e.g. gold alloy plating) as the connector material of the fingers as taught by Tomita. Doing so would allow for remarkable resistance to corrosion and outstanding conductivity.
Regarding claim 9, Tomita discloses the semiconductor package according to claim 1. Tomita is silent regarding wherein the first electronic component is a System on Chip (SoC).
Akamatsu discloses (col. 1, lines 9-17) capability of structuring one system on one chip, example is (Fig. 2) a mother chip comprising multiple functions.
Artisans in the art would have appreciated a system on chip reducing physical footprint and simplifying circuit board design. Thus it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the mother chip comprising multiple functions taught by Akamatsu into the first chip of Tomita to increase effective communication bandwidth of the package.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable by Tomita (US 20010002179 A1) in view of Akamatsu (US 5983331 A) and Chen (US 20080290486 A1)
Regarding claim 7, Tomita in view of Akamatsu discloses the semiconductor package according to claim 6. Tomita is silent regarding: a molding compound encapsulating the first electronic component, the second electronic component, the plurality of first bond wires, the plurality of second bond wires, the plurality of third bond wires, and the plurality of fourth bond wires.
Chen discloses (Fig. 18, ¶¶ [0069-0070]) a system-in-package (400) comprising chips bonding together using bond pads and bond wires, (¶ [0073]) the entire assembly is encapsulated by a molding compound (420).
Artisans in the art would have appreciated encapsulating multiple chips and interconnections into a single package will deliver the functions of an entire subsystem in the footprint of one component. As such it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the package encapsulation of Chen to the package of Tomita-Akamatsu to secure interconnections and prevent movement or fatigue under vibration or handling.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable overTomita (US 20010002179 A1) in view of Chen (US 20080290486 A1)
Regarding claim 8, Tomita discloses the semiconductor package according to claim 1. Tomita is silent regarding: a plurality of connecting elements on the second surface of the carrier substrate.
Chen discloses (Fig. 18, ¶¶ [0069, 0071]) a system-in-package (400) comprising chips bonding together using bond pads and bond wires, and the exposed bottom side connecting to a ground layer such as analog ground of the PCB, which can prevent digital signal noise from affecting the analog signal path.
Artisans in the art would have appreciated that in a system-in-package, the other side of the substrate can be allocated for power and ground distribution. As such it would have been obvious to one of ordinary skill int the art before the effective filing date of the invention to apply the grounding connection to the chip from the other side of the package substrate as disclosed by Chen to the package of Tomita to safely and efficiently distribute power and ground to different signal types in the package.
Claim(s) 11-16, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable by Tomita (US 20010002179 A1) in view of Wang (US 20120110402 A1) and Kim (US 20150378885 A1) and Shin (US 20220139432 A1) and
Regarding claim 11, Tomita discloses A semiconductor package, comprising: a carrier substrate (board, ¶ [0054]) comprising a first surface and a second surface opposite to the first surface; a first electronic component (10) and a second electronic component (20) mounted on the first surface of the carrier substrate in a side-by-side manner, wherein the second electronic component comprises at least a lower DRAM die and an upper DRAM die stacked on the lower DRAM die in a stepwise manner (Tomita does not teach the second chip is a stacked chip), wherein the first electronic component is provided with a plurality of high-speed signal pads (31, Tomita does not teach high-speed) along a first side directly facing the second electronic component, wherein the plurality of high-speed signal pads comprises a group of first data (DQ) (a portion of 31) pads arranged in a first sector adjacent to the first side, and a group of second data (DQ) (another portion of 31) pads arranged in a second sector adjacent to the first sector,
Tomita is silent regarding the pads of the first chip is high-speed, the second chip comprises an upper Dram and a lower Dram, wherein the lower DRAM die is provided with a plurality of third data (DQ) pads along a second side in proximity to the first electronic component, and the upper DRAM die is provided with a plurality of fourth data (DQ) pads along a third side in proximity to the first electronic component; a plurality of first bond wires directly connecting the group of first DQ pads in the first sector of the first electronic component to the plurality of third DQ pads of the lower DRAM die; and a plurality of second bond wires directly connecting the group of second DQ pads in the second sector of the first electronic component to the plurality of fourth DQ pads of the upper DRAM die.
Wang discloses (¶ [0006]) for a chip operates at very high frequency, high-speed I/O pads are used to facilitate testing rate for system on chip testing. Artisans in the art would have appreciated a system on chip comprises multiple functional blocks, enabling smaller physical size and higher operating frequencies. As such high-speed I/O pads can accommodate high-frequency ICs to drive and receive signals with sufficient bandwidth to preserve the high-frequency content. Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the system on chip (SOC) of Wang for the first chip of Tomita to achieve a high frequency IC. Substituting Tomita’s first chip with Wang’s SOC for Tomita would result in the respective pads of the first chip are high-speed I/O pads. Doing so would allow for signal integrity and system performance of the IC.
Tomita discloses the second chip as a memory chip but does not disclose the second chip comprises an upper Dram and a lower Dram.
Kim discloses (Fig. 1) a main chip (120) connecting a memory chip (110) wherein the memory chip comprises multiple chips (111) through data, command, address, and control pads; Shin discloses Fig. (1) memory chips are stepwise stacked. Artisans in the art would have appreciated adding a memory chip directly to a chip package is widely done to save space, improve performance, and reduce power use while integrating multiple functions into one module. Thus, it would have been obvious to one of ordinary skill in the art before the filing date of the invention to duplicate the memory chip of Tomita such that the duplication would have similar interconnection arrangement as the original and be stacked up stepwise with the original to increase the package’s functional capacity, memory bandwidth, data throughput, and system design flexibility. The modification of Tomita’s memory chip would result in a stepwise stack of memory chip wherein the memory chip individually connecting the main chip through data pads.
Regarding claim 12, Tomita in view of Wang, Kim and Shin discloses the semiconductor package according to claim 11. Kim further discloses (Fig. 1) wherein the first electronic component is further provided with a plurality of first command/address (CA) pads (Fig. 2) within a side sector that is juxtaposed with the first sector and the second sector along the first side directly facing the second electronic component, and the lower DRAM die is further provided with a plurality of second command/address (CA) pads along (Fig. 3) the second side directly facing the first electronic component, wherein the plurality of first CA pads is directly and electrically connected to the second CA pads through a plurality of third bond wires.
Tomita discloses the data pads connecting the main chip to the memory chip but does not include the command/address pads. Kim discloses the main chip connecting to the memory chip through multiple functional pads, data, command, address, and control pads. As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the main chip of Tomita with the main chip of Kim to achieve a fully functional chip package. As for the first sector, second sector, side sector of pads, where the parts (data pads, C/A pads on a chip) of a claim are disclosed in the prior art, it is not inventive to rearrange the parts (along the sides of the chip) through routine optimization. MPEP 2144.04
As such it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to rearrange the pads in such a way that the shortest possible bonding wire is achieved to reduce electrical resistance and improve performance.
Regarding claim 13. Tomita in view of Wang, Kim and Shin discloses the semiconductor package according to claim 12. Tomita further discloses (Fig. 1) wherein the first electronic component is further provided with a plurality of first power/ground pads (Vcc, Vss) in an elongated sector in front of the side sector and the first sector along the first side.
Regarding claim 14, Tomita in view of Wang, Kim and Shin The semiconductor package according to claim 13. Tomita further discloses (Fig. 1) wherein the plurality of first power/ground pads is directly and electrically connected to a plurality of first gold fingers (inner lead 42 denoting Vcc, Vss on the center top of of package 40, Tomita does not disclose “gold inner lead 42”) on the first surface of the carrier substrate through a plurality of fourth bond wires (bond wires connecting Vcc, Vss of logic chip 10 to inner leads 42).
While Tomita does not disclose inner leads (42) as gold fingers, Tomita discloses the lead lines 44 connecting data signals between the first and second chips as gold. Artisans in the art would have appreciated that gold fingers can be used to make reliable connections in a lead frame because they can provide low contact resistance and corrosion protection, as such it would have been obvious to one of ordinary skill in the art before the filing date of the invention to select gold (e.g. gold alloy plating) as the connector material of the fingers as taught by Tomita. Doing so would allow for remarkable resistance to corrosion and outstanding conductivity.
Regarding claim 15, Tomita in view of Wang, Kim, and Shin discloses the semiconductor package according to claim 14. Tomita further discloses (Fig. 1) wherein the second electronic component (modified memory package with staircase stacking of memory chips) is further provided with a plurality of second power/ground pads (Vcc, Vss) between the third DQ pads and the first CA pads.
Regarding claim 16, Tomita in view of Wang, Kim and Shin discloses the semiconductor package according to claim 15. Tomita further discloses (Fig. 1) wherein the plurality of second power/ground pads (Vcc, Vss) is directly and electrically connected to a plurality of second gold fingers (inner lead 42 denoting Vcc, Vss on the center top of of package 40, Tomita does not disclose “gold inner lead 42”) on the first surface of the carrier substrate through a plurality of fith bond wires (bond wires connecting Vcc, Vss of memory chip 20 to inner leads 42).
While Tomita does not disclose inner leads (42) as gold fingers, Tomita discloses the lead lines 44 connecting data signals between the first and second chips as gold. Artisans in the art would have appreciated that gold fingers can be used to make reliable connections in a lead frame because they can provide low contact resistance and corrosion protection, as such it would have been obvious to one of ordinary skill in the art before the filing date of the invention to select gold (e.g. gold alloy plating) as the connector material of the fingers as taught by Tomita. Doing so would allow for remarkable resistance to corrosion and outstanding conductivity.
Regarding claim 19, Tomita in view of Wang, Kim and Shin discloses the semiconductor package according to claim 11. The modified package of Tomita-Kim would allow for a combination of data pads and command/address pads, making it a System on Chip (SoC).
Regarding claim 20, Tomita in view of Wang, Kim and Shin discloses the semiconductor package according to claim 11. The modified package of Tomita and Kim would result in the side sector being contiguous with the first sector and the second sector.
Claim(s) 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable by Tomita (US 20010002179 A1) in view of Wang (US 20120110402 A1) and Kim (US 20150378885 A1), Shin (US 20220139432 A1) and Chen (US 20080290486 A1)
Regarding claim 17, Tomita in view of Wang, Kim, and Shin discloses the semiconductor package according to claim 16 further comprising. Tomita is silent regarding a molding compound encapsulating the first electronic component, the second electronic component, the plurality of first bond wires, the plurality of second bond wires, the plurality of third bond wires, the plurality of fourth bond wires, and the plurality of fifth bond wires.
Chen discloses (Fig. 18, ¶¶ [0069-0070]) a system-in-package (400) comprising chips bonding together using bond pads and bond wires, (¶ [0073]) the entire assembly is encapsulated by a molding compound (420).
Artisans in the art would have appreciated encapsulating multiple chips and interconnections into a single package will deliver the functions of an entire subsystem in the footprint of one component. As such it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the package encapsulation of Chen to the package of Tomita-Wang-Kim-Shin to secure interconnections and prevent movement or fatigue under vibration or handling.
Regarding claim 18, Tomita in view of Wang, Kim and Shin discloses the semiconductor package according to claim 11. Tomita is silent regarding: a plurality of connecting elements on the second surface of the carrier substrate.
Chen discloses (Fig. 18, ¶¶ [0069, 0071]) a system-in-package (400) comprising chips bonding together using bond pads and bond wires, and the exposed bottom side connecting to a ground layer such as analog ground of the PCB, which can prevent digital signal noise from affecting the analog signal path.
Artisans in the art would have appreciated that in a system-in-package, the other side of the substrate can be allocated for power and ground distribution. As such it would have been obvious to one of ordinary skill int the art before the effective filing date of the invention to apply the grounding connection to the chip from the other side of the package substrate as disclosed by Chen to the package of Tomita to safely and efficiently distribute power and ground to different signal types in the package.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Cusack (US 20070187814 A1) and Chung (US 20230116312 A1) disclose a main chip connecting a memory chip through functional pads.
Conclusion
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/DTH/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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