Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of claim(s) to be treated in this office action:
a. Independent: 2 and 12
b. Pending: 2-21
Claim 1 has been canceled and claims 2-21 have been added through preliminary amendments.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) is submitted on 2/12/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 7, 9-14, 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 11468963).
Regarding independent claim 2, Su discloses a system (Figs. 1-7C) comprising:
a memory controller (Fig. 4 shows control logic 450) configured to transmit data and a first error correction code (Fig. 4 and (28) describes a first error correction code (ECC) circuit 431, a data register 440, and a transmission interface 470) to a memory device (410, 420 and 440 together forms a memory device; Fig. 4);
the memory device coupled to the memory controller (Fig. 4 shows the connectivity), the memory device comprising:
a plurality of memory blocks, each memory block including a plurality of memory cells (Fig. 4 and (28) describes memory cell array 410 has a plurality of memory pages. Herein, the page data may be divided into a plurality of chunk data (equivalent to memory blocks);
a buffer configured to store the data (data register 440; Fig. 4) and the first error correction code (Fig. 1 and (9) describes that first error correction operation in step S130 is performed on chunk data having a small size, the number of error bits that may occur in a single piece of chunk data may not be large); and
error correction circuitry configured to:
detect and correct an error in the data stored in the buffer to generate corrected data (Fig. 1 and (9) describes that in step S130, a first error correction (error correction code, ECC) operation is performed on the plurality of chunk data and corresponding parity data in sequence and a plurality of corrected chunk data are respectively generated); and
generate a second error correction code (Fig. 1 and (11) describes that in step S140, a second error correction operation can be performed on the page data and corresponding parity data to generate corrected page data);
at least one memory block of the plurality of memory blocks being configured to store the corrected data from the buffer and the second error correction code (Figs. 3B-4 shows data flowing to and from (double sided arrow) buffer 440 into memory cell array through page buffer);
the error correction circuitry being further configured to detect and correct another error in the corrected data using the second error correction code to generate twice-corrected data (Fig. 1 and (11) describes step S140); and
the at least one memory block of the plurality of memory blocks being further configured to store the twice-corrected data (Figs. 3B-4 shows data flowing to and from (double sided arrow) buffer 440 into memory cell array through page buffer).
Regarding claim 3, Su discloses all the elements of claim 2 as above and further the first error correction code comprises a first hamming code ((10) describes that first error correction operation in step S130 may be implemented through the Hamming code manner).
Regarding claim 4, Su discloses all the elements of claim 2 as above and further the error correction circuitry is configured to correct a third error occurring after transmission while the corrected data is stored in the buffer ((32) describes that memory device 400 may further include a third ECC circuit 433. The third ECC circuit 433 is coupled between the control logic 450 and the data register 440. The third ECC circuit 433 can perform another error correction operation on the page data).
Regarding claim 7, Su discloses all the elements of claim 2 as above and further the error correction circuitry is further configured to perform multiple encoding and decoding operations on the data, the corrected data, or the twice-corrected data to detect at which process or operation an error occurs (Fig. 4 shows three ECC circuits that comprise encoders and decoders).
Regarding claim 9, Su discloses all the elements of claim 2 as above and further the second error correction code is generated by segmenting the corrected data into multiple sections and performing a one's complement checksum over the multiple sections (Figs. 3A-3B and (18)-(19) describes page data may be divided into a plurality of chunk data CH0 to CH5 and an error correction (ECC) operation is performed on one piece of chunk data CH0 to CH5 in sequence in step S361).
Regarding claim 10, Su discloses all the elements of claim 2 as above and further the twice-corrected data and the second error correction code are stored in separate portions of the at least one memory block (In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) (Claims to a hydraulic power press which read on the prior art except with regard to the position of the starting switch were held unpatentable because shifting the position of the starting switch would not have modified the operation of the device.); In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975) (the particular placement of a contact in a conductivity measuring device was held to be an obvious matter of design choice).
Regarding claim 11, Su discloses all the elements of claim 2 as above and further each memory block of the plurality of memory blocks includes one or more pages, and the one or more pages in each memory block includes the plurality of memory cells in each respective memory block (Fig. 4 and (28) describes that memory cell array 410 has a plurality of memory pages and is coupled to the page buffer 420. When a read operation is performed on the memory cell array 410, one memory page in the memory cell array 410 may be selected for reading, and page data which is read out is temporarily stored in the page buffer 420. Herein, the page data may be divided into a plurality of chunk data).
Claims 12-14, 17 and 19-20 recite the exact same limitations of device claims 2-4, 7 and 9-11 except drafted in method format and henceforth rejected the same way.
Claims 5-6 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 11468963) in view of Khadiwala et al. (US 20170132079).
Regarding claim 5, Su discloses all the elements of claim 2 as above and Su discloses buffers as cache memory. Here examiner asserts that cache memory is primarily made of SRAM (Static Random-Access Memory). Some modern designs may use specialized, faster-than-usual DRAM (eDRAM) for larger, lower-level caches.
Also, Khadiwala further the buffer comprises a volatile memory device selected from the group consisting of SRAM and DRAM ([0081] and [0088] describes random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, cache memory, and/or any device that stores digital information).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Khadiwala to modified Su in order to rebuild and verify data slices in a dispersed storage network as taught by Khadiwala ([0005]).
Regarding claim 6, Su discloses all the elements of claim 2 as above and through Khadiwala further the second error correction code comprises a checksum ([0038] describes that error encoding parameters may further include slicing information (e.g., the number of encoded data slices that will be created for each data segment) and/or slice security information (e.g., per encoded data slice encryption, compression, integrity checksum, etc.)).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Khadiwala to modified Su in order to rebuild and verify data slices in a dispersed storage network as taught by Khadiwala ([0005]).
Claims 15-16 recite the exact same limitations of device claims 5-6 except drafted in method format and henceforth rejected the same way.
Claims 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 11468963) in view of Hwang et al. (US 20210026734).
Regarding claim 8, Su discloses all the elements of claim 2 as above and through Hwang further the at least one memory block includes a spare area, wherein the spare area is configured to store at least an error correction code ([0081] describes spare memory cells for ECC).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Hwang to modified Su in order to provide a storage device securing improved reliability while increasing the number of bits to be written in one memory cell as taught by Hwang ([0005]).
Claim 18 recite the exact same limitations of device claim 8 except drafted in method format and henceforth rejected the same way.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Su (US 11468963) in view of Ryu et al. (US 20210311821).
Regarding claim 21, Su discloses all the elements of claim 12 as above and through Ryu further the storing the twice-corrected data includes storing the twice-corrected data in a page, and the page includes a plurality of volatile memory cells ([0007] describes a memory cell array which includes a plurality of memory cell rows, each row including a plurality of volatile memory cells; an ECC engine; an error information register; and a control logic circuit configured to control the ECC engine to perform a read-modify-write operation by: reading data corresponding to a first codeword from a sub-page in a first memory cell row among the plurality of memory cell rows based on an access address and a command from an external device; performing an ECC decoding on the data to generate an error generation signal in response to detecting an error in the first codeword; correcting the detected error in the first codeword; and writing a corrected first codeword in a first memory location corresponding to the sub-page; and the semiconductor memory device further includes a storage memory to store the first address designating the first memory location as a hard fault or a progressive fault and its associated corrected data).
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teachings of Ryu to modified Su in order to provide mechanism for using error correction code (ECC) information in repairing defective cells as taught by Hwang ([0002]).
Conclusion
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/SULTANA BEGUM/Primary Examiner, Art Unit 2824 4/2/2026