DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 09/23/2024. Claims 1-11 are presented for examination and have been considered below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over (US 8,555,140 B2, hereafter "Gunnam") and further in view of (US 8,127,209 B1, hereafter "Zhang").
Claim 1: Gunnam teaches a decoder circuit (e.g. item 110 (FIG. 1), 500 (FIG. 5), 800 (FIG. 8), 1200 (FIG. 12), 1300 (FIG. 13), 1400 (FIG. 14). col. 4:20-24; col. 10:30-38; col. 20:30-40), comprising:
a memory circuit (e.g. Q Init 410, P memory, Q FIFO 524/1224, FS memory 1204/1304), for receiving and temporarily storing an input data (e.g. col. 10, lines 4-10; col. 20, lines 52-54; col. 22, lines 10-13);
a variable node circuit, coupled to the memory circuit, for receiving data of a specific codeword of the input data to generate or update a variable-to-check message and generate a log-likely ratio to a syndrome calculation circuit (e.g. Variable node processing is performed by VNU array 404 (FIG. 4A) and by the variable node logic in decoders 500, 1200, etc. Variable-to-check message = Q message (equations (7), (9)-(12), (38)). Log-likelihood ratio = P<sub>n</sub> (equation (8)); it is used for hard decision and syndrome check. The syndrome check (Ĥ H<sup>T</sup> = 0) is explicitly performed; thus a syndrome calculation circuit is functionally present. col. 7:20-40 (variable node processing, eqs. 7, 8); col. 7:45-52 (hard decision & syndrome check); col. 9:55-57 (VNU array));
a variable-to-check circuit, coupled to the variable node circuit, for converting the variable-to-check message from a variable node domain into a check node domain to generate a converted variable-to-check message (e.g. Cyclic shifters/permuters (e.g., 514, 1214) perform the required domain conversion. Equation (10) explicitly shows the cyclic shift operation: [\bar{Q}_{l,n}^{(i)}]^{S(l,n)} – the Q vector is shifted according to the shift coefficient s(l,n). This aligns the variable node messages for check node processing in the layered decoding schedule. col. 8:4-10; col. 11:1-9; Eq. (10); FIG. 5, 12);
a check node circuit, coupled to the variable-to-check circuit, for performing a minimization calculation based on the converted variable-to-check message to generate a check-to-variable message (e.g. Check Node Unit (CNU) micro-architecture 200 (FIG. 2A, 2B) performs the min-sum or offset min-sum algorithm. It finds the two minimum magnitudes (M1, M2) of the incoming Q messages and generates the R message (check-to-variable). CNU arrays (502, 702, 1202) implement this for all check nodes in parallel. col. 8:65-col. 9:67; FIG. 2A, 2B; Eqs. (4)-(6), (11); col. 10:66-col. 11:2);
a check-to-variable circuit, coupled to the check node circuit, for converting the check-to-variable message from the check node domain to the variable node domain to generate a converted check-to-variable message, to make the variable node circuit based on the converted check-to-variable message perform a sum calculation to update the variable-to-check message and performing another sum calculation to update the log-likely ratio (e.g. Inverse shifting is performed using the delta shift (difference of successive shift coefficients) – e.g., via shifter 514 or 1214. Equation (12): [ \bar{P}n^{l} ]^{S(l,n)} = [\bar{Q}{l,n}^{(i)}]^{S(l,n)} + \bar{R}_{l,n}^{(i)} – the shifted P sum is used for the next layer. The variable node circuit then performs: Sum calculation to update variable-to-check message: Q_new = P_new_shifted – R_old (eq. 38). Sum calculation to update log-likelihood ratio: P_new = Q_old + R_new (eq. 35) and the final decision P_n (eq. 8). col. 8:13-19 (delta shift); col. 11:14-20; Eqs. (12), (35), (38), (8)); and
the syndrome calculation circuit, coupled to the variable node circuit, for performing a hard decision based on the log-likely ratio to determine whether to flip information of at least one bit in the specific codeword to generate an output codeword (e.g. Hard decision is defined: \hat{x}_n = 0 if P_n ≥ 0, else 1. Syndrome check evaluates \hat{x} H^T = 0. If the syndrome is zero, the decoded codeword is output; otherwise further iterations are performed (thus bits may be “flipped” relative to the received values in subsequent iterations). A dedicated syndrome calculation circuit is implied by this parity-check operation. col. 7:45-52; col. 6:5-10 (syndrome check)).
Not explicitly taught by Gunnam is that the memory circuit based on the input data, a shortening setting and a puncturing setting is arranged to store multiple data portions of the input data in multiple corresponding storage positions according to a decoding calculation schedule of the decoder circuit, and to respectively free up a space of at least one first storage position for at least one shortened data portion indicated by the shortening setting and free up a space of at least one second storage position for at least one punctured data portion indicated by the puncturing setting.
However, Zhang teaches a decoder system incorporating a lookup table (608/700) used to store and track specific conditions (trapping set patterns) related to the data being decoded (col. 6, l. 15-67; Fig. 6). This teaches the skilled artisan that a lookup table is a known, effective tool for managing auxiliary state information about a codeword during the decoding process.
Therefore, it would have been obvious to a skilled artisan, before the effective filing date of the claimed invention, to adapt the lookup table taught by the Zhang for use in Gunnam's decoder. The problem of handling shortened and punctured bits in rate-compatible LDPC codes was well-known. Thus, a skilled artisan, seeking to efficiently manage memory in Gunnam's architecture for such codes, would recognize that using a lookup table (as shown in Zhang) to flag which memory positions correspond to shortened or punctured bits (freeing those positions from storing real channel data) is a logical and straightforward application of a known memory management technique to a known decoder structure. The "freeing up" of space is a direct and inherent consequence of marking a position as containing shortened/punctured data.
As per claim 6, the claimed features are rejected similarly to claim 1 above.
Claim 2: Gunnam and Zhang teach the decoder circuit of claim 1, wherein the memory circuit comprises: a receiving unit, for receiving the input data (implicit in I/O port 106 and initialization logic - Gunnam), but fail to teach that the shortening setting, and the puncturing setting; a lookup table, coupled to the receiving unit; and a memory unit, coupled to the receiving unit, for storing the multiple data portions of the input data; when the receiving unit stores the multiple data portions of the input data in the multiple corresponding storage positions within the memory unit according to the decoding calculation schedule, the receiving unit is arranged to simultaneously generate and note a first information in multiple fields corresponding to the multiple corresponding storage positions in the lookup table; when the receiving unit controls the memory unit to free up the space of the at least one first storage position for the at least one shortened data portion indicated by the shortening setting, the receiving unit is arranged to simultaneously generate and note a second information in at least one field corresponding to the at least one shortened data portion in the lookup table; and, when the receiving unit controls the memory unit to free up the space of the at least one second storage position for the at least one punctured data portion indicated by the puncturing setting, the receiving unit is arranged to simultaneously generate and note the second information in at least one field corresponding to the at least one punctured data portion in the lookup table.
However, Gunnam teaches a control unit (528) that generates and uses scheduling parameters stored in memory and Zhang teaches a specific lookup table (700) with fields corresponding to trapping sets, where information (syndrome and error patterns) is noted (col. 6, l. 40-67; Fig. 7). This directly teaches the claimed "lookup table... arranged to simultaneously generate and note... information in... fields." Therefore, given the known need to handle shortened/punctured bits, it would have been obvious to implement Gunnam's memory management using the lookup table structure of Zhang. Instead of noting trapping set patterns, the skilled artisan would simply note "first information" (valid data) and "second information" (shortened/punctured) in the table fields corresponding to storage positions, as this is a conventional use of a flag table in memory systems.
Claim 3: Gunnam and Zhang teach the decoder circuit of claim 2, wherein the variable node circuit reads information noted in a specific field from the lookup table to determine whether to retrieve a specific data portion from a specific storage position of the memory circuit which corresponds to the specific field, to perform a decoding calculation. For instance, Gunnam teaches a variable node circuit (VNU 404, variable node processing described in equations) that reads data (Q, P) from memory to perform calculations and Zhang teaches a decoder that reads from a lookup table to determine subsequent actions (e.g., whether to apply a correction pattern). Therefore, it would be an obvious optimization for the variable node circuit to consult the lookup table (a known element Zhang, now repurposed to track data validity) before accessing main memory. This avoids unnecessary memory reads for invalid/shortened/punctured data, improving efficiency, which is routine design goal.
Claim 4: Gunnam and Zhang teach the decoder circuit of claim 3, wherein when the information noted in the specific field, read by the variable node circuit from the lookup table, indicates the first information, the variable node circuit is arranged to read the specific data portion from the specific storage position in the memory unit corresponding to the specific field to perform the decoding calculation; and, when the information noted in the specific field, read by the variable node circuit from the lookup table, indicates the second information, the variable node circuit is arranged to directly use a reference data portion having a preset reference value to perform the decoding calculation without reading the memory unit. For instance, Gunnam teaches that the variable node processing equations (e.g., col. 7, eq. 7) show the VNU uses channel LLR values (L_n) or updated P messages. The handling of "null blocks" by setting messages to fixed values (e.g., "positive infinity") is disclosed (col. 8, l. 60-65). Therefore, combining Gunnam's teaching of using fixed values for null data with the lookup-table-driven decision mechanism from Zhang makes it obvious to implement the claimed two-path logic: read real data if the table indicates "first information," or substitute a preset reference value (like LLR=0 for punctured bits or a high-confidence value for shortened bits) if the table indicates "second information."
Claim 5: Gunnam and Zhang teach the decoder circuit of claim 4, wherein the memory unit comprises multiple physical sub-memories, and writing of the multiple physical sub-memories is controlled by the receiving unit; for writing of a specific address, the receiving unit is arranged to write a specific data portion of the input data into a storage position of a specific physical sub-memory among the multiple physical sub-memories, and to control the memory unit to close a writing operation of another specific physical sub-memory and to free up a space of a storage position of the another specific physical sub-memory for the shortening setting or the puncturing setting. For instance, Gunnam teaches a Memory organized in banks or arrays (e.g., CNU array 502, sign FIFO 510, multiple Q Init buffers). The architecture is highly parallel and implies partitioned memory. And implementing the memory unit with multiple physical sub-memories is a common technique for parallel access and efficient design. Therefore, tt would be obvious to a skilled artisan to organize Gunnam's memory this way. Furthermore, using control logic (guided by the lookup table from Zhang) to disable writes to certain sub-memory positions corresponding to shortened/punctured bits is a standard power and management optimization in memory design.
As per claims 7-10, the claimed features are rejected for the same reasons as Claims 2-5. The method steps of using and reading the lookup table, and the specific logic flows, are the obvious functional implementations of the apparatus features derived from the combined teachings of Gunnam and Zhang.
Claim 11 is directed to a flash memory controller comprising an encoder and the decoder circuit of claim 1. Gunnam teaches the application of the LDPC decoder in data storage systems (col. 4, l. 50-54: "applied to data storage systems where LDPC encoded data is stored on a storage medium"). Therefore, it would have been obvious to integrate the obvious combination of Gunnam's decoder (modified with Zhang's lookup table for rate compatibility) into a flash memory controller. Gunnam explicitly mentions data storage as a key application field. Flash memory is a prevalent type of non-volatile storage. Combining a known decoder architecture (adapted for rate-compatibility as argued above) with a memory controller for its intended field of use is a routine integration by a skilled artisan.
Conclusion
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/11/2026