DETAILED ACTION
This action is responsive to the amendments filed July 9, 2026. Claims 1-7 are pending. Claims 1-7 are amended. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on May 4, 2026. This IDS has been considered.
Specification
Applicant’s amendment to the title of the invention is acknowledged and accepted. The objection to the title has been withdrawn.
Claim Objections
Claims 1 and 7 are objected to because of the following informalities:
The claims recite “storing the test voltage in the sensing latch” (emphasis added). Digital latches store data which is also supported by the specification at para. 60. This appears to be a possible minor translation error. It is suggested to change “voltage” to “data” for clarity purposes.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sabde et al. (US 20160012904; "Sabde" – of record), in view of Li et al. (US 11309035; “Li”), and further in view of Missiroli (US 20170243653 – of record).
Regarding independent claim 1, Sabde discloses a method of performing a test operation on a memory device, the method comprising:
initializing a memory block and a page buffer connected to the memory block (Fig. 6; See also para. 63; “A physical page, such as the page 60, is a group of memory cells enabled to be sensed or programmed in parallel. This is accomplished by a corresponding page of sense amplifiers 212.”);
wherein initializing the memory block and the page buffer comprises:
erasing the memory block (para. 95; "This can be done by erasing all blocks of an array");
and wherein detecting defects of the memory block comprises:
Sabde discloses detecting defects, including by erasing blocks but is silent as to detecting after an initialize step, and as to the detect recipe.
However, Li teaches and detecting defects of the memory block after initializing the memory block and the page buffer (col. 26, ln. 36-38; “Since the memory cells are in the erased state at the start of the operation, this type of NAND string is identified as being problematic”. See also Abstr. “A short circuit detection operation includes a channel pre-clean phase”, “followed by a bit line pre-charge phase”, “followed by a bit line discharge phase”, “followed by a sensing phase which identifies the short circuited NAND strings”).
applying a test voltage to a selected line among word lines and select lines in the memory block connected to the bit line (col. 19, ln. 15-19; “The presence of a word line-to-channel short circuit in the NAND string 902 allows a positive voltage on WL95 to charge up the channel of this NAND string. The charge on the channel is conveyed to the bit line contact 912 and to the bit line BL2.”);
transmitting a voltage of the bit line to the sensing node (col. 19, ln. 58-62; “The XXL, BLC and BLS transistors are turned on to provide a path from the bit lines to the respective sense circuits. Each sense circuit can detect a current and/or voltage in a respective NAND string based on an amount of voltage decay of a sense node”);
and storing the test voltage in the sensing latch according to a voltage of the sensing node ( Step 825 includes setting data in latches to identify short circuited and non-short circuited NAND strings, based on the sensing. For example… a respective sense node latch 172 can be set to 1 or 0, for example, by the comparison circuit 175 based on whether the memory cell is in a conductive or non-conductive state, respectively).
Sabde discloses erasing the block as part of the defect determination and sense amplifiers and latches on the bit lines, but is silent with respect to initializing the page buffer and discharging the sensing node connected between that latch and the bit line. Li discloses detecting a word line to channel short after the cells are in an erased state including applying a positive voltage to the selected word line, coupling that voltage to the bit line if a short exists, but is silent with respect to resetting the sensing latch and discharging the sensing node as the steps that precede that detection.
However, Missiroli teaches resetting a sensing latch of the page buffer (para. 20; “In the pre-charging period t1, firstly, a sense latch 31 is reset so that a node QS has a low voltage level”.);
and wherein detecting defects of the memory block comprises:
discharging a sensing node connected between the sensing latch and a bit line connected to the page buffer (Abstr.; "a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node during an evaluation period");
Sabde, Li and Missiroli are from the same field of endeavor as applicant's invention directed to the operation of NAND flash memories with page buffers. Sabde is a NAND on-chip screen for word line and select line shorts/leaks. It erases blocks as part of that screen and uses sense amplifiers and latches on the bit lines, but it determines defects by whether a later erase/program/read succeeds. It does not evaluate a discharged sensing node after a selected-line bias.
Li detects word line to channel shorts by applying a positive voltage to the word line after the cells are already erased, coupling that voltage onto the bit line if the short exists, connecting the bit line to a sense node, and setting sense-node latch 172. Li is silent as to performing the erase and silent as to resetting the latch and discharging SEN as named initialize steps.
Missiroli is a conventional NAND current-sensing page buffer: reset sense latch 31, discharge SEN, couple BL to SEN, store the result in the latch. It is silent as to a short-detection test voltage on a selected line and silent as to erase as part of that test.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to, starting from Sabde’s erase of the block, use Missiroli’s page-buffer setup (reset latch, discharge SEN, BL-to-SEN, store) to read the bit line, and apply Li’s selected-WL bias / reverse-charge detect once the block is erased, because Li is the on-chip method that turns that erased state into a latch result for a WL-to-channel short. Doing so would yield the predictable result of the recited initialize-then-detect method.
Regarding claim 2, Sabde, Li and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein resetting the sensing latch includes storing initial data in the sensing latch (para. 61; "when the pre-charging period t1 starts, the sense latch 31 is reset". It is noted that this limitation appears to be a tautology as the specification recites (para. 61) that the "initial data" is merely whatever value is in the sensing latch after the reset.).
Regarding claim 3, Sabde, Li and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein discharging the sensing node includes discharging the sensing node and the bit line by forming a current path between the sensing node and the bit line and a ground terminal (Fig. 2 where it illustrates a path from the bit-line (BL) to the sensing node (SEN) with at least one discharge path to ground. See also Abstr.; "a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node").
Regarding claim 4, Sabde, Li and Missiroli combined disclose the limitations of claim 1.
As applied, Li further discloses wherein applying the test voltage includes setting the test voltage applied to the selected line to a positive voltage (col. 19, ln. 15-17; “The presence of a word line-to-channel short circuit in the NAND string 902 allows a positive voltage on WL95 to charge up the channel of this NAND string.” See also col. 26, ln. 32-34; “the reverse charged is caused by the word line voltage, Vread, reaching the bit line through the short circuit.”).
Regarding claim 5, Sabde, Li and Missiroli combined disclose the limitations of claim 1.
As applied, Li further discloses wherein transmitting of the voltage of the bit line to the sensing node includes increasing the voltage of the bit line when a short defect exists between the selected line and a memory cell or select transistor connected to the selected line (Fig. 10 where it illustrates Vbl_sc. See also col. 24, ln. 29-36; “A leaky bit line is subject to reverse charging from a leaky word line… Vbl_sc increases to a first level L1 at t0a due to Vwl increasing to Vdd. Vsgd and Vsgs also increase to Vdd… Vbl_sc increases further to a second level L2 at t0b when Vwl increases from Vdd to Vread, e.g., 8 V.”)
and maintaining the bit line at a discharge level when the short defect does not exist between the selected line and the memory cell or the select transistor (col. 22, ln. 65-67; “the voltages of BL0 and BL4 remain at the discharged level V2 as depicted in FIG. 10 for Vbl_good in the sensing phase 1003.”)
Regarding claim 6, Sabde, Li and Missiroli combined disclose the limitations of claim 3.
As applied, Missiroli further discloses transmitting the voltage of the bit line to the sensing node includes blocking the current path (para. 54; "The third transistor M3 is turned off during the pre-charging period to isolate or separate the sensing node SEN from the first node CSO. In other words, the first charging path and the second charging path are separated during the pre-charging period by controlling the third transistor M3". It is noted that Missiroli's formed current path then subsequently blocking that current path is the same known control sequence as in the instant application (e.g.: Blocked during pre-charge, conditionally opened during evaluation, results latched) and its execution would be an obvious engineering design choice which would yield predictable results in defect detection.
Regarding claim 7, Sabde, Li and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein storing the test voltage in the sensing latch according to the voltage of the sensing node includes storing the test data having the same value as initial data in the sensing latch when the voltage of the sensing node is maintained at a discharge level (para. 20; “In the pre-charging period t1, firstly, a sense latch 31 is reset so that a node QS has a low voltage level,”. See also para. 77; “If the sensing node SEN has been discharged, the sensing transistor M5 is enabled, and the voltage level of the input node QS of the sensing latch 31 is raised. Otherwise, the voltage level of the input QS of the sensing latch 31 is maintained.”
and storing the test data having a value different from that of the initial data in the sensing latch (para. 77; "If the sensing node SEN has been discharged, the sensing transistor M5 is enabled, and the voltage level of the input node QS of the sensing latch 31 is raised.
Missiroli’s latch flips when SEN discharges, not when it rises (increases to a positive voltage).
However, as applied Li further discloses when the voltage of the sensing node increases to a positive voltage (Fig. 8, step 825. See also col. 20, ln. 16-19; “a respective sense node latch 172 can be set to 1 or 0, for example, by the comparison circuit 175 based on whether the memory cell is in a conductive or non-conductive state, respectively.”
It is noted that Missiroli flips QS when SEN discharges. The claim flips the stored data when SEN rises. Li is the reference that puts the sense node on the high/positive side when the selected line is shorted to the channel and on the decayed/discharged side when it is not. The level of SEN which is coded for each is merely a routine engineering choice and does not patentably distinguish the claim from the prior art.
Response to Arguments
Applicant's arguments filed July 9, 2026, have been fully considered but they are not persuasive.
The rejection of claims 1–7 is maintained as a new ground under 35 U.S.C. § 103 over Sabde in view of Li and further in view of Missiroli. Li (as a new reference) is applied to amended claim 1’s new sequence requirement that defects be detected after initializing the memory block and the page buffer.
Applicant’s only argument on the merits is that Sabde’s erase is the defect detection operation (erase disturb / erase fail after stress, Sabde para. 89-95), not a prior initializing step, and that Missiroli does not supply an initialize-then-detect sequence.
The argument attacks the references individually. Sabde is not required to teach the page-buffer initialize or the selected-line / sensing-node / latch detect. Missiroli is not required to teach the short-detection test. Li is not required to teach the erase. The test is what the combination teaches. See MPEP 2145.
Amended claim 1 increased the scope of the claim by adding a required sequence but did not add a new act. The rejection for claim 1 in the previous Office action already recited erasing the memory block, resetting the sensing latch, discharging the sensing node, applying a test voltage to a selected line, transmitting the bit-line voltage to the sensing node, and storing a result in the sensing latch. The amendment merely groups those same acts under a sequence of “initializing” and “detecting … after initializing.” The word “initializing” is a label for the three acts listed under it. It does not require that the erase have a different purpose than the erase in Sabde para. 95, and it does not forbid an erase that also yields pass/fail information. What the claim requires is that the erase, latch reset, and sensing-node discharge occur, and that the detect acts (test voltage on a selected line, bit line to the sensing node, store in the latch) occur after those initialize acts.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
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