DETAILED ACTION
This action is responsive to the application filed September 23, 2024. Claims 1-7 are pending. Claim 1 is independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on September 23, 2024. This IDS has been considered.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Test Operation for Detecting Word Line to Channel Shorts in NAND Flash Memory
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Sabde et al. (US 20160012904; "Sabde"), in view of Missiroli (US 20170243653).
Regarding independent claim 1, Sabde discloses a method of performing a test operation on a memory device, the method comprising:
erasing a memory block (para. 95; "A post-stress detection sequence can then follow. The exemplary embodiment for a detection sequence uses an erase disturb test to detect the word line to word line shorts from adjacent blocks. This can be done by erasing all blocks of an array");
applying a test voltage to a selected line among word lines and select lines in the memory block connected to the bit line (para. 10; "The method performs word line to select gate stress operation on the first word line and the first select gate line, including applying a set of stress voltage levels to the first word line and first select gate line". It is understood that stress voltages are analogous to a test voltage.);
Sabde recites latching sensed results (para 63; "The sensed results are latched in a corresponding set of latches 214") but is silent with respect to explicitly labeling the latch as a sensing latch.
However, Missiroli teaches resetting a sensing latch (para. 61; "when the pre-charging period t1 starts, the sense latch 31 is reset".);
discharging a sensing node connected between the sensing latch and a bit line (Abstr.; "a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node");
transmitting a voltage of the bit line to the sensing node (Fig. 2 where it illustrates a path from the bit-line (BL) to the sensing node (SEN). It is well understood in the art that memory page buffer circuits necessarily transmit the bit line voltage to the sense node.);
and storing the test voltage in the sensing latch according to a voltage of the sensing node (para. 77; "If the sensing node SEN has been discharged, the sensing transistor M5 is enabled, and the voltage level of the input node QS of the sensing latch 31 is raised. Otherwise, the voltage level of the input QS of the sensing latch 31 is maintained.").
Sabde and Missiroli are from the same field of endeavor as applicant's invention directed to the operation of NAND flash memories with page buffers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sabde's test operation for detecting short defects in NAND memory blocks, with the teachings of Missiroli's latched current-sensing page buffer architecture. Doing so would provide improved sensitivity to small current differences on the bit line thereby improving the accuracy and reliability of on-chip short defect detection in NAND memory devices.
Regarding claim 2, Sabde and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein the resetting of the sensing latch includes storing initial data in the sensing latch (para. 61; "when the pre-charging period t1 starts, the sense latch 31 is reset". It is noted that this limitation appears to be a tautology as the specification recites (para. 61) that the "initial data" is merely whatever value is in the sensing latch after the reset.).
Regarding claim 3, Sabde and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein the discharging of the sensing node includes discharging the sensing node and the bit line by forming a current path between the sensing node and the bit line and a ground terminal (Fig. 2 where it illustrates a path from the bit-line (BL) to the sensing node (SEN) with at least one discharge path to ground. See also Abstr.; "a third switching circuit arranged between the first node and a sensing node and configured to discharge the sensing node").
Regarding claim 4, Sabde and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein the applying of the test voltage includes setting the test voltage applied to the selected line to a positive voltage (para. 104; "modes that apply a stress (high voltage) on word lines". As noted in the rejection for claim 1 above, Missiroli's stress voltages are analogous to the test voltages of the instant application).
Regarding claim 6, Sabde and Missiroli combined disclose the limitations of claim 3.
As applied, Missiroli further discloses the transmitting of the voltage of the bit line to the sensing node includes blocking the current path (para. 54; " The third transistor M3 is turned off during the pre-charging period to isolate or separate the sensing node SEN from the first node CSO. In other words, the first charging path and the second charging path are separated during the pre-charging period by controlling the third transistor M3". It is noted that Missiroli's formed current path then subsequently blocking that current path is the same known control sequence as in the instant application (e.g.: Blocked during pre-charge, conditionally opened during evaluation, results latched) and its execution would be an obvious engineering design choice which would yield predictable results in defect detection.
Regarding claim 7, Sabde and Missiroli combined disclose the limitations of claim 1.
As applied, Missiroli further discloses wherein the storing of the test voltage in the sensing latch according to the voltage of the sensing node includes
storing the test data having the same value as initial data in the sensing latch when the voltage of the sensing node is maintained at a discharge level, and storing the test data having a value different from that of the initial data in the sensing latch when the voltage of the sensing node increases to a positive voltage (para. 77; "If the sensing node SEN has been discharged, the sensing transistor M5 is enabled, and the voltage level of the input node QS of the sensing latch 31 is raised. Otherwise, the voltage level of the input QS of the sensing latch 31 is maintained." It is noted that Missiroli's sensing latch logic level is complimentary from that of the instant application. However, this is merely a common inversion of sensing polarity which is an arbitrary engineering design choice because the specification does not disclose any particular technical advantage to one chosen logic polarity over the other.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sabde et al. (US 20160012904; "Sabde"), in view of Missiroli (US 20170243653), and further in view of Li et al. (US 20120008384; "Li").
Regarding claim 5, Sabde and Missiroli combined disclose the limitations of claim 1.
Sabde and Missiroli disclose short detection using current sensing operations within the page buffer but are silent with regard to explicit detection of word line leakage to the channel.
However, Li teaches wherein the transmitting of the voltage of the bit line to the sensing node includes
increasing the voltage of the bit line when a short defect exists between the selected line and a memory cell or select transistor connected to the selected line, and maintaining the bit line at a discharge level when the short defect does not exist between the selected line and the memory cell or the select transistor (para 52; "In one implementation the detection of the conduction current relative to a threshold current is accomplished by examining the rate the conduction current is discharging through the capacitance of the bit line". It is well understood in the art that all shorts necessarily increase the conduction current between the shorted elements and that Missiroli's page buffer architecture is well suited to detect a conduction current on the bit line.
Sabde and Missiroli combined, along with Li are from the same field of endeavor as the instant application directed to defect detection in NAND flash memories with page buffers. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Sabde's test operation for detecting short defects in NAND memory blocks, with the teachings of Missiroli's latched current-sensing page buffer architecture and with Li's voltage change on the bit line due to a short. Doing so provides predictable results by the use of known techniques in the detection of word line to channel shorts which would improve reliability of NAND flash memory.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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