DETAILED ACTION
This office action is in response to the application filed on 9/23/2024. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/23/2024, 4/2/2025 and 12/8/2025 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 11, 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Wang (US 9,870,975)
With respect to Claim 1, Lin shows (Fig. 18,20-21,23,25-26) most aspects of the current invention including a semiconductor package comprising:
a lower package (100) including a lower semiconductor chip, (38) a molding layer (48) on a side surface of the lower semiconductor chip, a conductive post (36) in the molding layer and having a top surface having a concave shape (see Fig 20), a lower redistribution pattern (layers 54,60) under the lower semiconductor chip and the molding layer and electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution (204) above the lower semiconductor chip and the molding layer, electrically connected the conductive post;
an upper package (200) on the lower package, the upper package including an upper semiconductor chip (202);
wherein the upper redistribution includes an upper insulating layer (dielectric of layer 204) and an upper redistribution pattern (206),
wherein the conductive post is on an inner wall of the molding layer, a first portion of the inner wall of the molding layer contacting a sidewall of the conductive post and a second portion of the inner wall of the molding layer extending vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post, (see Fig 20; second portion of the inner wall of the molding layer (covered by layer 30A) is vertically coplanar with the sidewall of the conductive post and the first portion of the inner wall of the molding layer; also see Fig 26 second portion of the inner wall of the molding layer (covered by layer 24) is vertically coplanar with the sidewall of the conductive post and the first portion of the inner wall of the molding layer)
wherein a lowermost level of the upper insulating layer (dielectric of layer 204) of upper redistribution is vertically above a top surface of the molding layer facing the upper package
Furthermore, although Lin shows the wherein the upper redistribution pattern is electrically connected to a top surface of the conductive post (by solder region 80), Lin fails to show wherein the upper redistribution pattern is contacting the top surface of the conductive post.
On the other hand, and in the same field of endeavor, Wang teaches (Fig. 1N) a semiconductor package comprising, a lower package including a lower semiconductor chip (220) a molding layer (222) on a side surface of the lower semiconductor chip, a conductive post (210) in the molding layer, an upper redistribution above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes an upper insulating layer (dielectric 400) and an upper redistribution pattern (conductive pad and conductive layer 402), wherein the upper redistribution pattern (conductive layer 402) is contacting the top surface of the conductive post. Wang teaches the upper redistribution pattern is used to provide a direct electrical connection between the conductive post and the upper redistribution pattern (column t lines 8-25).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the upper redistribution pattern is contacting the top surface of the conductive post, in the device of Lin, as taught by Wang because the upper redistribution pattern is used to provide a direct electrical connection between the conductive post and the upper redistribution pattern.
With respect to Claim 2, Lin shows (Fig. 18,20-21,23,25-26) wherein a corner portion of the molding layer slopes downward from the top surface of the molding layer to the second portion of the inner wall of the molding layer (see Fig 23)
With respect to Claim 11, Lin shows (Fig. 18,20-21,23,25-26) wherein a lowermost level of the corner portion of the molding layer is vertically above an uppermost level of the top surface of the conductive post.
With respect to Claim 13, Lin shows (Fig. 18,20-21,23,25-26) wherein the conductive post has a bottom surface having a flat shape.
Claims 3 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Wang (US 9,870,975) and in further view of Huang (US 2019/0067249).
With respect to Claim 3, Lin in view of Wang shows most aspects of the current invention including wherein a corner portion of the molding layer is between the top surface of the molding layer and the inner wall of the molding layer and is chamfered or rounded. However, the combination of references do not show wherein the upper insulating layer is on the corner portion of the molding layer.
On the other hand, and in the same field of endeavor, Huang teaches (Fig. 1H,2B) a semiconductor package comprising, a lower package (PKG1) including a lower semiconductor chip (20), a molding layer (22) on a side surface of the lower semiconductor chip, a conductive post (14) in the molding layer, an upper redistribution above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes insulating layers (dielectric 38 and dielectric in layer 30) and an upper redistribution pattern (conductive layers 33,34). Further Huang teaches a corner portion of the molding layer is between the top surface of the molding layer and the inner wall of the molding layer and is chamfered or rounded and the insulating layer (dielectric 38) is on the corner portion of the molding layer. Huang teaches the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the upper insulating layer is on the corner portion of the molding layer, in the device of Lin in view of Wang, as taught by Huang because the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
Claims 4 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Wang (US 9,870,975) and in further view of Lee (US 2020/0185352).
With respect to Claim 4, Lin in view of Wang shows most aspects of the current invention. However, the combination of references do not show wherein the upper redistribution pattern includes an upper conductive line pattern and an upper conductive via pattern, the upper conductive line pattern being on a top surface of the upper insulating layer and the upper conductive via pattern being electrically connected to the upper conductive line pattern, and wherein the upper conductive via pattern contacts the top surface of the conductive post.
On the other hand, and in the same field of endeavor, Lee teaches (Fig. 14) a semiconductor package comprising, a lower package (10) including a lower semiconductor chip (130), a molding layer (140) on a side surface of the lower semiconductor chip, a conductive post (122) in the molding layer, an upper redistribution (150) above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes upper insulating layers (dielectrics 152) and an upper redistribution pattern (conductive layers 155,157). Further Lee teaches wherein the upper redistribution pattern includes an upper conductive line pattern (155) and an upper conductive via pattern (157), the upper conductive line pattern being on a top surface of the upper insulating layer and the upper conductive via pattern being electrically connected to the upper conductive line pattern, and wherein the upper conductive via pattern contacts the top surface of the conductive post. Lee teaches the upper conductive via pattern is used to provide a direct electrical connection between the conductive post and the upper redistribution pattern.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the upper redistribution pattern includes an upper conductive line pattern and an upper conductive via pattern, the upper conductive line pattern being on a top surface of the upper insulating layer and the upper conductive via pattern being electrically connected to the upper conductive line pattern, and wherein the upper conductive via pattern contacts the top surface of the conductive post, in the device of Lin in view of Wang, as taught by Lee because the upper conductive via pattern is used to provide a direct electrical connection between the conductive post and the upper redistribution pattern.
Claims 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Wang (US 9,870,975) and in further view of Lee (US 2020/0185352) and in further view of Huang (US 2019/0067249).
With respect to Claim 5, Lin in view of Wang and in further view of Lee shows most aspects of the current invention. However, the combination of references do not show wherein the insulating layer is on the second portion of the inner wall of the molding layer.
On the other hand, and in the same field of endeavor, Huang teaches (Fig. 1H,2B) a semiconductor package comprising, a lower package (PKG1) including a lower semiconductor chip (20), a molding layer (22) on a side surface of the lower semiconductor chip, a conductive post (14) in the molding layer, an upper redistribution above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes insulating layers (dielectric 38 and dielectric in layer 30) and an upper redistribution pattern (conductive layers 33,34). Further Huang teaches a first portion of the inner wall of the molding layer contacting a sidewall of the conductive post and a second portion of the inner wall of the molding layer extending vertically above the top surface of the conductive post, wherein the insulating layer (dielectric 38) is on the second portion of the inner wall of the molding layer. Huang teaches the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the insulating layer is on the second portion of the inner wall of the molding layer, in the device of Lin in view of Wang and Lee, as taught by Huang because the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
With respect to Claim 6, Lee teaches wherein the upper conductive via pattern is horizontally spaced apart from the inner wall of the molding layer (see Fig. 16)
With respect to Claim 7, Huang teaches (Fig. 1H,2B) wherein the insulating layer is between the upper conductive pattern and the inner wall of the molding layer.
With respect to Claim 8, Lee teaches (Fig. 14) wherein the upper conductive via pattern has a tapered width increasing away from the top surface of the conductive post
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Wang (US 9,870,975) and in further view of Shin (US 2011/0049695).
With respect to Claim 12, Lin in view of Wang shows most aspects of the current invention. However, the combination of references do not show wherein the molding layer is on a top surface of the semiconductor chip.
On the other hand, and in the same field of endeavor, Shin teaches (Fig. 8) a semiconductor package comprising, a lower package (10) including a lower semiconductor chip (122), a molding layer (144) on a side surface of the lower semiconductor chip, a conductive post (166) in the molding layer, wherein the molding layer is on a top surface of the semiconductor chip. Shin teaches doing so to environmentally protect the semiconductor device from external elements (par 44).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the molding layer is on a top surface of the semiconductor chip in the device of Lin in view of Wang, as taught by Shin to environmentally protect the semiconductor device from external elements.
Claims 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Huang (US 2019/0067249).
With respect to Claim 14, Lin shows (Fig. 18,20-21,23,25-26) most aspects of the current invention including a semiconductor package comprising:
a lower package (100) including a lower semiconductor chip, (38) a molding layer (48) on a side surface of the lower semiconductor chip, a conductive post (36) in the molding layer and having a top surface having a concave shape (see Fig 20), a lower redistribution pattern (layers 54,60) under the lower semiconductor chip and the molding layer and electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution (204) above the lower semiconductor chip and the molding layer, electrically connected the conductive post;
an upper package (200) on the lower package, the upper package including an upper semiconductor chip (202);
wherein the conductive post is on an inner wall of the molding layer, a first portion of the inner wall of the molding layer contacting a sidewall of the conductive post and a second portion of the inner wall of the molding layer extending vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post, (see Fig 20; second portion of the inner wall of the molding layer (covered by layer 30A) is vertically coplanar with the sidewall of the conductive post and the first portion of the inner wall of the molding layer; also see Fig 26 second portion of the inner wall of the molding layer (covered by layer 24) is vertically coplanar with the sidewall of the conductive post and the first portion of the inner wall of the molding layer)
wherein the upper redistribution includes an upper insulating layer (dielectric of layer 204) and an upper redistribution pattern (206),
Lin fails to show wherein the upper insulating layer of the upper redistribution including a protrusion on the second portion of the inner wall of the molding layer, wherein a bottom surface of the protrusion of the upper insulating layer is coplanar with the top surface of the conductive post, and wherein a width of the protrusion of the upper insulating layer at the same vertical level as a level of the bottom surface of the molding layer is greater than a width of the protrusion of the upper insulating layer at the same vertical level as a level of the second portion of inner wall of the molding layer.
On the other hand, and in the same field of endeavor, Huang teaches (Fig. 1H,2B) a semiconductor package comprising, a lower package (PKG1) including a lower semiconductor chip (20), a molding layer (22) on a side surface of the lower semiconductor chip, a conductive post (14) in the molding layer, an upper redistribution above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes insulating layers (dielectric 38 and dielectric in layer 30) and an upper redistribution pattern (conductive layers 33,34). Further Huang teaches wherein the upper insulating layer of the upper redistribution including a protrusion on the second portion of the inner wall of the molding layer (portion of molding layer extending downward in recess 28a,28b), wherein a bottom surface of the protrusion of the upper insulating layer (see Fig 2c; dotted line coplanar with conductive post 14) is coplanar with the top surface of the conductive post, and wherein a width of the protrusion of the upper insulating layer at the same vertical level as a level of the bottom surface of the molding layer is greater than a width of the protrusion of the upper insulating layer at the same vertical level as a level of the second portion of inner wall of the molding layer. Huang teaches the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the upper insulating layer of the upper redistribution including a protrusion on the second portion of the inner wall of the molding layer, wherein a bottom surface of the protrusion of the upper insulating layer is coplanar with the top surface of the conductive post, and wherein a width of the protrusion of the upper insulating layer at the same vertical level as a level of the bottom surface of the molding layer is greater than a width of the protrusion of the upper insulating layer at the same vertical level as a level of the second portion of inner wall of the molding layer, in the device of Lin, as taught by Huang because the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
With respect to Claim 20, Lin shows (Fig. 18,20-21,23,25-26) most aspects of the current invention including a semiconductor package comprising:
a lower package (100) including a lower semiconductor chip, (38) a molding layer (48) on a side surface of the lower semiconductor chip, a conductive post (36) in the molding layer and having a top surface having a concave shape (see Fig 20), a lower redistribution pattern (layers 54,60) under the lower semiconductor chip and the molding layer and electrically connecting the lower semiconductor chip to the conductive post, and an upper redistribution (204) above the lower semiconductor chip and the molding layer, electrically connected the conductive post;
an upper package (200) on the lower package, the upper package including an upper semiconductor chip (202);
wherein the conductive post is on an inner wall of the molding layer, a first portion of the inner wall of the molding layer contacting a sidewall of the conductive post and a second portion of the inner wall of the molding layer extending vertically above the top surface of the conductive post, wherein the first and second portions of the inner wall of the molding layer are vertically coplanar with each other and with the sidewall of the conductive post, (see Fig 20; second portion of the inner wall of the molding layer (covered by layer 30A) is vertically coplanar with the sidewall of the conductive post and the first portion of the inner wall of the molding layer; also see Fig 26 second portion of the inner wall of the molding layer (covered by layer 24) is vertically coplanar with the sidewall of the conductive post and the first portion of the inner wall of the molding layer)
wherein a corner portion of the molding layer slopes downward from the top surface of the molding layer to the second portion of the inner wall of the molding layer
wherein the upper redistribution includes an upper insulating layer (dielectric of layer 204) and an upper redistribution pattern (206),
wherein a corner portion of the molding layer is between the top surface of the molding layer and the inner wall of the molding layer
Lin fails to show wherein the upper insulating layer of the upper redistribution including a protrusion on the second portion of the inner wall of the molding layer, and wherein a corner portion of the molding layer is coplanar with the corner portion of the protrusion of the upper insulating layer.
On the other hand, and in the same field of endeavor, Huang teaches (Fig. 1H,2B) a semiconductor package comprising, a lower package (PKG1) including a lower semiconductor chip (20), a molding layer (22) on a side surface of the lower semiconductor chip, a conductive post (14) in the molding layer, an upper redistribution above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes insulating layers (dielectric 38 and dielectric in layer 30) and an upper redistribution pattern (conductive layers 33,34). Further Huang teaches wherein the upper insulating layer of the upper redistribution including a protrusion on the second portion of the inner wall of the molding layer (portion of molding layer extending downward in recess 28a,28b), wherein a corner portion of the molding layer is coplanar with the corner portion of the protrusion of the upper insulating layer. Huang teaches the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the upper insulating layer of the upper redistribution including a protrusion on the second portion of the inner wall of the molding layer, and wherein a corner portion of the molding layer is coplanar with the corner portion of the protrusion of the upper insulating layer, in the device of Lin, as taught by Huang because the insulating layer on the corner portion of the molding layer is used to fill the space between the lower package structure and the upper package structure and to surround a portion of the conductive post and a connection layer, providing protection against external damage
Claims 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Huang (US 2019/0067249) and Lee (US 2020/0185352).
With respect to Claim 15, Lin in view of Huang, shows most aspects of the current invention. However, the combination of references do not show wherein the upper redistribution pattern includes an upper conductive line pattern and an upper conductive via pattern, the upper conductive line pattern is on a top surface of the upper insulating layer and the upper conductive via pattern is electrically connected to the upper conductive line pattern, and wherein the upper conductive via pattern extends in the protrusion of the upper insulating layer and contacts the top surface of the conductive post.
On the other hand, and in the same field of endeavor, Lee teaches (Fig. 14) a semiconductor package comprising, a lower package (10) including a lower semiconductor chip (130), a molding layer (140) on a side surface of the lower semiconductor chip, a conductive post (122) in the molding layer, an upper redistribution (150) above the lower semiconductor chip and the molding layer, electrically connected the conductive post, wherein the upper redistribution includes upper insulating layers (dielectrics 152) and an upper redistribution pattern (conductive layers 155,157). Further Lee teaches wherein the upper redistribution pattern includes an upper conductive line pattern (155) and an upper conductive via pattern (157), the upper conductive line pattern is on a top surface of the upper insulating layer and the upper conductive via pattern is electrically connected to the upper conductive line pattern, and wherein the upper conductive via pattern extends in an opening of the molding layer and contacts the top surface of the conductive post. Lee teaches the upper conductive via pattern is used to provide a direct electrical connection between the conductive post and the upper redistribution pattern.
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the upper redistribution pattern includes an upper conductive line pattern and an upper conductive via pattern, the upper conductive line pattern is on a top surface of the upper insulating layer and the upper conductive via pattern is electrically connected to the upper conductive line pattern, and wherein the upper conductive via pattern extends in the protrusion of the upper insulating layer and contacts the top surface of the conductive post, in the device of Lin in view of Huang, as taught by Lee because the upper conductive via pattern is used to provide a direct electrical connection between the conductive post and the upper redistribution pattern.
With respect to Claim 16, Huang teaches (Fig. 1H,2B) wherein a corner portion of the protrusion of the upper insulating layer slopes downward from the bottom surface of the upper insulating layer to a sidewall of the protrusion of the upper insulating layer
With respect to Claim 17, Huang teaches (Fig. 1H,2B) wherein a corner portion of the protrusion of the upper insulating layer is between the bottom surface of the upper insulating layer and a sidewall of the protrusion of the upper insulating layer and is chamfered or rounded.
With respect to Claim 18, Huang teaches (Fig. 1H,2B) wherein a corner portion of the molding layer is between the top surface of the molding layer and the inner wall of the molding layer, and is coplanar with the corner portion of the protrusion of the upper insulating layer
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2019/0103362) in view of Huang (US 2019/0067249) and in further view of Shin (US 2011/0049695).
With respect to Claim 19, Lin in view of Huang, shows most aspects of the current invention. Furthermore, Lin shows a vertical length of the conductive post is greater than a vertical length of the lower semiconductor chip and is less than a vertical length of the molding layer (see Fig. 18,20). However, the combination of references do not show wherein the molding layer is on a top surface of the semiconductor chip.
On the other hand, and in the same field of endeavor, Shin teaches (Fig. 8) a semiconductor package comprising, a lower package (10) including a lower semiconductor chip (122), a molding layer (144) on a side surface of the lower semiconductor chip, a conductive post (166) in the molding layer, wherein the molding layer is on a top surface of the semiconductor chip. Shin teaches doing so to environmentally protect the semiconductor device from external elements (par 44).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have the arrangement of wherein the molding layer is on a top surface of the semiconductor chip in the device of Lin in view of Wang, as taught by Shin to environmentally protect the semiconductor device from external elements.
Allowable Subject Matter
Claims 9-10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/Q. B./
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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