DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 2-21 are presented for examination.
Priority
Acknowledgement is made of applicant's claim for domestic priority under 35 U.S.C. § 120, through utility this application is a Continuation of U.S. Patent Application No. 18/233,250, filed August 11, 2023, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, which is a Continuation of U.S. Patent Application No. 17/852,272, filed June 28, 2022, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, now U.S. Patent No. 11,734,106, which is a Continuation of U.S. Patent Application No. 16/872,929, filed May 12, 2020, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, now U.S. Patent No. 11,385,959, which is a Continuation of U.S. Patent Application No. 15/829,682, filed December 1, 2017, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, now U.S. Patent No. 10,664,344, which is a Continuation of U.S. Patent Application No. 15/250,677, filed August 29, 2016, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, now U.S. Patent No. 9,836,349, which is a Non-Provisional that claims priority to U.S. Patent Application No. 14/285,481, filed May 22, 2014, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, now U.S. Patent No. 9,430,324, which is a Non-Provisional that claims priority to U.S. Provisional Application No. 61/827,383, filed May 24, 2013, entitled MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING, all of which are incorporated herein by reference in their entirety.
Information Disclosure Statement
The references listed in the information disclosure statement (IDS) submitted have been considered. The submission complies with the provisions of 37 CFR 1.9 /. Form PTO-1449 is signed and attached hereto.
Specification
The specification is objected to because:
The Cross-Reference to Related Applications section in paragraph [0001] of the specification does not provide the status of U.S. Patent Application No. 18/233,250 (i.e., now U.S. Patent No. 12,111,723).
Drawings
The formal drawings are accepted.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A non-statutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on non-statutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 2-21 rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,111,723.
For example, claim 2 of the present application teaches “a memory module, comprising: a substrate; at least one integrated circuit (IC) memory device disposed on the substrate; and an IC buffer chip, the IC buffer chip including: secondary interface circuitry to receive read data during a read operation from the at least one IC memory device along secondary data paths, the read data from the at least one IC memory device comprising a known error bit; comparison circuitry to compare information associated with the read data to known failure information; data insertion circuitry to insert a previously stored data bit as a replacement for the known error bit in the read data to generate corrected read data; and primary interface circuitry to transfer the corrected read data to a memory controller along primary data paths. \
Whereas claim 1 of U.S. Patent No. 12,111,723 teaches “a memory module, comprising :a substrate; at least one integrated circuit (IC) memory device disposed on the substrate; and an IC buffer chip, the IC buffer chip including: primary interface circuitry to receive write data from a memory controller along primary data paths; comparison circuitry to compare information associated with the write data to known failure information; data extraction circuitry, if the comparison circuitry identifies a correlation between the information associated with the write data and the known failure information, to extract a portion of the write data corresponding to the correlation and to store the portion of the write data in substitute storage; and secondary interface circuitry to transfer the write data for storage in the at least one memory device along secondary data paths”.
[0030] For subsequent write operations to the faulty address, the address logic 318 uses a tag comparison circuit 324 to compare incoming addresses to known defective addresses stored in the address memory 320. When a "hit" is detected, indicating a matching address to a known faulty location, the bit designated for writing to the faulty cell is extracted via an extraction circuit 326 (disposed on each error decoder), and directed to the assigned substitute cell in the redundant memory 322. For data reads, an insertion circuit 328 accesses the bit in the redundant memory 322 and inserts it into the proper read data word location prior to the read data word being transferred across the DQ data path 308. For some embodiments, compare circuitry (not shown) may be employed to compare the previously determined defective bit with the repair bit to more accurately determine the presence of a "hard" or "soft" error. In this manner, if a "soft" error was involved, and did not repeat, the spare bit location may be used elsewhere, thereby freeing redundant resources.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application and the U.S. Patent No. 12,111,723 claim IC buffer chip, interface circuits for receiving and transferring reading and writing data, and a comparison circuitry for comparing information associated with the known failure information. Claim 2 of the instant application claim variously the same limitations/steps as that of claim 1 of the U.S. Patent No. 12,111,723. There is a mere difference between the claims and claim 2 of the instant application comprises receiving and transferring read data when comparing information associated with the read data to a known failure information while claim 1 of the U.S. Patent No. 12,111,723 receiving and transferring write data when comparing information associated with the write data to known failure information. However, such difference is deemed obvious to those skilled in the art in claim drafting to seek a well-rounded protection for a disclosed invention in drafting claims when comparing information associated with the read and write data to a known failure information. The examiner would like to point out that claim 2 of the present application is substantially the same of claim 1 of U.S. Patent No. 12,111,723. One is just an embodiment of the other and the claims are obvious variations of each other and not patentably distinct.
“A latter patent claim is not patentably distinct from an earlier patent claim if the latter claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896, 225USPQ at 651 (affirming a holding of obvious-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel independent claims of the instant application have corresponding issues with the independent claims of U.S. Patent No. 12,111,723 are also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Other parallel dependent claims have corresponding issues with the independent claims of U.S. Patent No. 12,111,723 are also rejected under non-statutory obviousness-type double patenting for the same rationales discussed above.
Allowable Subject Matter
The rejection(s) under obvious type non-statutory double patenting for claims 2-21 would be in condition for allowance if a properly executed Terminal Disclaimer is filed by the applicant, set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Vogelsang et al. (US: 9,037,949) teaches a dynamic random-access memory (DRAM) array is configured for selective repair and error correction of a subset of the array. Error- correcting code (ECC) is provided to a selected subset of the array to protect a row or partial row of memory cells where one or more weak memory cells are detected. By adding a sense amplifier stripe to the edge of the memory array, the adjacent edge segment of the array is employed to store ECC information associated with the protected subsets of the array.
Gorman et al. (US: 2014/0143619) describes testing and repair of the memory comprise determining whether the read memory data is correct. For example, all of the read memory data bits or basic data (e.g., the full data width) may be compared against expected data stored in the data comparator and repair system. Any mis-compares may trigger repair of the failing memory, e.g., the data comparator and repair system may be configured to use extra/redundant memory blocks in an attempt to repair the failing memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112