DETAILED ACTION
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on 9/23/24. These drawings are acceptable.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “configuration module” in claims 1, 7-9 and 11-12.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
Paragraph [0017] on page 6 of the present specification states “It is appreciated that each of the module and/or controllers in the system 100 can be one or more computing units or devices, each with software instructions stored in a storage unit such as a non-volatile memory of the computing unit for practicing one or more processes.”
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim 20 recites the following “means for storing” “means for designating” these are being interpreted as being the following:
“means for storing” = the on-chip memory – figure 1 element 104
“means for designating” = the OCM configuration module – figure 1 element 102.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 6, 10, 13, 14, are 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motwani US 2016/0156372.
As per claim 1, Motwani substantially teaches the claimed apparatus, comprising: an on-chip memory (OCM) (Fig 6 SOC element 1660) comprising a plurality of memory banks, wherein each of the plurality of memory banks is configured to store both data and a set of code words used for error correction of the data (Abstract); and an OCM configuration module configured to designate and configure a first set of the plurality of memory banks in the OCM to support a first error detection and/or correction mechanism (Paragraph [0071] encoding data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion; storing each codeword of the set in a separate memory bank of a memory block); and designate and configure a second set of the plurality of memory banks in the OCM to support a second error detection and/or correction mechanism (Paragraph [0071] encoding the data portions of each codeword of the set with a second error correction scheme, the combined codeword having a data portion and a corresponding parity portion; and storing the corresponding parity portion of the combined codeword in an additional memory bank of the memory block).
While Motwani does not explicitly teach a configuration module the memory controller of Motwani performs the claimed functionality (Paragraph [0047] and Paragraph [0074 the memory controller including: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory die of the plurality NVM dies; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme) of the configuration module of claim 1 in the present application. Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application.
Claim 13 is the on-chip memory (OCM) claim corresponding to claim 1 and is rejected for the same reasoning.
Claim 14 is the method claim corresponding to claim 1 and is rejecting for the same reasoning.
Claim 20 is the system claim corresponding to claim 1 and is rejected for the same reasoning.
As per claim 2 Motwani teaches a memory controller to control access to at least one of the plurality of memory banks of the OCM, however it would be obvious to duplicate parts to perform the same function as the single memory controller of Motwani (Paragraph [0019]).
As per claim 5 Motwani teaches the first and/or the second error detection and/or correction mechanism is a parity mechanism (Paragraph [0022] Each codeword includes a data portion and a corresponding parity portion.).
As per claim 6, Motwani teaches the first set of the plurality of memory banks and/or the second set of the plurality of memory banks are continuous memory banks in the OCM (Paragraph [0032] Encoding scheme illustrates a logical partitioning of the memory dies, Fig 3).
As per claim 10 and 18 Motwani teaches one or more of the plurality of memory banks each comprise a plurality of memory instances configured to store data and a corresponding set of code words to support one of the first and the second error detection and/or correction mechanisms (Abstract ;encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme).
Claim(s) 3 11, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motwani US 2016/0156372 in view of Cho et al. US 2023/0178168.
As per claim 3, Motwani substantially teaches the claimed apparatus of claim 1 (see above) however Motwani does not teach that the memory type of the OCM is static random-access memory (SRAM). However in an analogous art Cho et al. teach an on chip error correctable memory device (Paragraph [0004]) where the memory is SRAM (Paragraph [0033]). Therefore it would have been obvious to a person having ordinary skill in the art to have used the SRAM of Cho et al. with the on-chip memory of Motwani. This would be obvious as both are directed to correcting on chip memory errors.
As per claim 11 and 19 Cho et al. teaches the OCM configuration module is configured to assign one or more of the plurality of memory instances to store one of: i) the data only, or ii) the code words only, and iii) both the data and the code words interleavingly (Paragraph [0099]).
As per claim 12 Motwani teaches the OCM configuration module is configured to assign certain un-used memory space between the data and the code words in each of one or more of the plurality of memory instances that store both the data and the code words (Paragraph [0033] generates a Parity Portion of Super Codeword which is stored in a data portion or region of the redundant memory bank).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motwani US 2016/0156372 in view of Casado et al. US 20140258805
As per claim 4, Motwani substantially teaches the claimed apparatus of claim 1 (see above) however Motwani does not teach the first and/or the second error detection and/or correction mechanism is a Single bit Error Correction Double bit Error Detection (SECDED) mechanism.
However in an analogous art Casado et al. teaches the first and/or the second error detection and/or correction mechanism is a Single bit Error Correction Double bit Error Detection (SECDED) mechanism (Paragraph [0012]). Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to use the SECDED of Casado et al. with the apparatus of Motwani as both are directed to error correction in memory chips (Paragraph [0055] SOC package).
Allowable Subject Matter
Claims 7-9 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
The prior arts of record teach:
US 11,048,583 to Hokenmaier et al. teach a memory device with one or more memory arrays, on-die error correction code (ECC) circuitry, and on-die bypass functionality for enabling or disabling the ECC circuitry, wherein: the bypass functionality is configurable such that the device can be used with or without ECC protection.
US 2013/0103991 to Evain et al. generating code words from data organized in binary words by application of asymmetric code introducing at least two different levels of protection, the first level of protection said to be high being associated with a first sub-group of bits of the code word and a second level of protection said to be low being associated with a second sub-group of the same word
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/ Primary Examiner, Art Unit 2111