Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 5/14/26 have been fully considered but they are not persuasive.
As per applicant’s argument “Motwani fails to teach or suggest that each of the plurality of memory banks is configured to store both data and a set of code words used for error correction of the data, as claimed.” Paragraph [0071] teaches “In another example, a method is provided which comprises: encoding data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion; storing each codeword of the set in a separate memory bank of a memory block; encoding the data portions of each codeword of the set with a second error correction scheme, the combined codeword having a data portion and a corresponding parity portion; and storing the corresponding parity portion of the combined codeword in an additional memory bank of the memory block.”
As per applicant’s argument “Motwani does not teach or suggest that different error correction schemes are designated and configured in the same memory banks” In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “in the same memory banks”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant also argues “Motwani fails to teach or suggest an OCM configuration module configured to designate and configure a first/second set of the plurality of memory banks in the OCM”. As stated in the previous office action: “While Motwani does not explicitly teach a configuration module the memory controller of Motwani performs the claimed functionality (Paragraph [0047] and Paragraph [0074] the memory controller including: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory die of the plurality NVM dies; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme) of the configuration module of claim 1 in the present application.”
Therefore, the arguments are not persuasive, and the previous rejection is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 5, 6, 10, 13, 14, are 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motwani US 2016/0156372.
As per claim 1, Motwani substantially teaches the claimed apparatus, comprising: an on-chip memory (OCM) (Fig 6 SOC element 1660) comprising a plurality of memory banks, wherein each of the plurality of memory banks is configured to store both data and a set of code words used for error correction of the data (Abstract); and an OCM configuration module configured to designate and configure a first set of the plurality of memory banks in the OCM to support a first error detection and/or correction mechanism (Paragraph [0071] encoding data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion; storing each codeword of the set in a separate memory bank of a memory block); and designate and configure a second set of the plurality of memory banks in the OCM to support a second error detection and/or correction mechanism (Paragraph [0071] encoding the data portions of each codeword of the set with a second error correction scheme, the combined codeword having a data portion and a corresponding parity portion; and storing the corresponding parity portion of the combined codeword in an additional memory bank of the memory block).
While Motwani does not explicitly teach a configuration module the memory controller of Motwani performs the claimed functionality (Paragraph [0047] and Paragraph [0074] the memory controller including: a first encoder to encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory die of the plurality NVM dies; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme) of the configuration module of claim 1 in the present application. Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application.
Claim 13 is the on-chip memory (OCM) claim corresponding to claim 1 and is rejected for the same reasoning.
Claim 14 is the method claim corresponding to claim 1 and is rejected for the same reasoning.
Claim 20 is the system claim corresponding to claim 1 and is rejected for the same reasoning.
As per claim 2 Motwani teaches a memory controller to control access to at least one of the plurality of memory banks of the OCM, however it would be obvious to duplicate parts to perform the same function as the single memory controller of Motwani (Paragraph [0019]).
As per claim 5 Motwani teaches the first and/or the second error detection and/or correction mechanism is a parity mechanism (Paragraph [0022] Each codeword includes a data portion and a corresponding parity portion.).
As per claim 6, Motwani teaches the first set of the plurality of memory banks and/or the second set of the plurality of memory banks are continuous memory banks in the OCM (Paragraph [0032] Encoding scheme illustrates a logical partitioning of the memory dies, Fig 3).
As per claim 10 and 18 Motwani teaches one or more of the plurality of memory banks each comprise a plurality of memory instances configured to store data and a corresponding set of code words to support one of the first and the second error detection and/or correction mechanisms (Abstract ;encode data with a first error correction scheme to generate a set of codewords, each codeword of the set having a data portion and a corresponding parity portion, and each codeword of the set to be stored in a separate memory bank of a memory block; and a second encoder to encode the data portions of each codeword of the set with a second error correction scheme).
Claim(s) 3 11, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motwani US 2016/0156372 in view of Cho et al. US 2023/0178168.
As per claim 3, Motwani substantially teaches the claimed apparatus of claim 1 (see above) however Motwani does not teach that the memory type of the OCM is static random-access memory (SRAM). However in an analogous art Cho et al. teach an on chip error correctable memory device (Paragraph [0004]) where the memory is SRAM (Paragraph [0033]). Therefore it would have been obvious to a person having ordinary skill in the art to have used the SRAM of Cho et al. with the on-chip memory of Motwani. This would be obvious as both are directed to correcting on chip memory errors.
As per claim 11 and 19 Cho et al. teaches the OCM configuration module is configured to assign one or more of the plurality of memory instances to store one of: i) the data only, or ii) the code words only, and iii) both the data and the code words interleavingly (Paragraph [0099]).
As per claim 12 Motwani teaches the OCM configuration module is configured to assign certain un-used memory space between the data and the code words in each of one or more of the plurality of memory instances that store both the data and the code words (Paragraph [0033] generates a Parity Portion of Super Codeword which is stored in a data portion or region of the redundant memory bank).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motwani US 2016/0156372 in view of Casado et al. US 20140258805
As per claim 4, Motwani substantially teaches the claimed apparatus of claim 1 (see above) however Motwani does not teach the first and/or the second error detection and/or correction mechanism is a Single bit Error Correction Double bit Error Detection (SECDED) mechanism.
However in an analogous art Casado et al. teaches the first and/or the second error detection and/or correction mechanism is a Single bit Error Correction Double bit Error Detection (SECDED) mechanism (Paragraph [0012]). Therefore it would have been obvious to a person having ordinary skill in the art at the time of filing of the present application to use the SECDED of Casado et al. with the apparatus of Motwani as both are directed to error correction in memory chips (Paragraph [0055] SOC package).
Allowable Subject Matter
Claims 7-9 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA H BRITT whose telephone number is (571)272-3815. The examiner can normally be reached Monday - Thursday 8-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at (571)270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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CYNTHIA H. BRITT
Primary Examiner
Art Unit 2111
/CYNTHIA BRITT/Primary Examiner, Art Unit 2111
Prosecution Insights