Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer et al. (US 10355475 and Kinzer hereinafter).
Regarding claim 1, Kinzer discloses an electronic device [fig. 6 and 8] comprising: a package base [830]; a gallium nitride (GaN)-based semiconductor device [ABSTRACT] attached to the package base, the GaN-based semiconductor device comprising: a first transistor [110] having a first gate terminal, a first source terminal and a first drain terminal; a second transistor [610] having a second gate terminal, a second source terminal and a second drain terminal, wherein the second drain terminal is coupled to the first gate terminal [a second drain terminal of 610 coupled to first gate of 110 as shown in fig. 6]; and a silicon-based semiconductor device [615, col 6 lines 21-41] attached to the package base. Kinzer described further an electrically insulative encapsulant at least partially encapsulating the package base [inherent with IC manufacturing], the GaN-based semiconductor device and the silicon-based semiconductor device [inherent]. Kinzer does not explicitly disclose the silicon-based semiconductor device including a control circuit arranged to turn on the second transistor when a voltage at the first gate terminal is less than a predetermined threshold voltage.
However, Kinzer shows in fig. 6 transistor 615 (a control circuit) turns on 610 when 615 is in a high-impedance state. This causes the gate of 610 to be at Vcc which causes 610 to short the gate of 110 to the source of 110 which causes 110 to be turned off due the gate of 110 being below the inherent Vgs on/off voltage (a predetermined threshold). It would have been obvious to one having ordinary skill in the art before the effective filing date to provide the control circuit arranged to turn on the second transistor when a voltage at the first gate terminal is less than a predetermined threshold voltage with the transistor 615 controlling transistors 610 and 110, in order to improve overvoltage protections in a switching circuit. See In re Preda, 159 USPQ 342 (CCPA, 1968).
Regarding claim 2, Kinzer discloses further wherein the control circuit is arranged to sense the voltage at the first gate terminal [gate of 615 sensing gate voltage of 110 through unlabeled resister on gate of 110] to determine when the voltage at the first gate terminal is less than the predetermined threshold voltage [col 9 lines 1-20].
Regarding claim 3, Kinzer discloses further wherein when the second transistor is turned on, the voltage at the first gate terminal is clamped to a preset voltage [col 6 line 59 – col 7 line 8].
Regarding claim 4, Kinzer discloses further [fig. 7] comprising a current flow control circuit [725, 750, 730 and related circuitry] arranged to receive an input signal [drain] and in response transmit a corresponding output signal to the first gate terminal [through 730].
Regarding claim 6, Kinzer discloses further wherein the control circuit further comprises a third transistor [730] having a third gate terminal, a third source terminal and a third drain terminal wherein the third source terminal is coupled to the first gate terminal [gate of 110] and the third drain terminal is coupled to the current flow control circuit [as shown].
Regarding claim 7, Kinzer discloses circuit [fig. 6] comprising: a first transistor [110] having a first gate terminal, a first source terminal and a first drain terminal; a second transistor [610] having a second gate terminal, a second source terminal and a second drain terminal, wherein the second drain terminal is coupled to the first gate terminal [as shown]; and a control circuit [615] arranged to turn on the second transistor when a voltage at the first gate terminal is less than a predetermined threshold voltage [610 turned on when 615 is off meaning 655 is low].
Regarding claim 8, Kinzer discloses further wherein the control circuit is arranged to sense the voltage at the first gate terminal [615 sensing gate voltage of 110] to turn on the second transistor [col 6 line 59 – col 7 line 8].
Regarding claim 9, Kinzer discloses further wherein when the second transistor is turned on, the voltage at the first gate terminal is clamped to a preset voltage [col 6 line 59 – col 7 line 8].
Regarding claim 10, Kinzer discloses further wherein the first and second transistors are disposed in a gallium nitride (GaN)-based die [col 6 lines 21-41].
Regarding claim 11, Kinzer discloses further wherein the control circuit is disposed in a silicon- based die [col 6 lines 21-41].
Regarding claim 12, Kinzer discloses further wherein the GaN-based die and the silicon-based die are packaged in a unitary semiconductor package [as shown in fig. 8].
Regarding claim 13, Kinzer discloses further [fig. 7] comprising a current flow control circuit [725, 750, 730 and related circuitry] arranged to receive an input signal [drain] and in response transmit a corresponding output signal to the first gate terminal [through 730].
Regarding claim 15, Kinzer discloses further comprising a third transistor [730] having a third gate terminal, a third source terminal and a third drain terminal wherein the third source terminal is coupled to the first gate terminal [gate of 110] and the third drain terminal is coupled to the current flow control circuit [as shown].
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer in view of Leong et al. (US 9698768 and Leong hereinafter.) further in view of Vos et al. (US 20160276954 A1 and Vos hereinafter.).
Regarding claim 5, Kinzer discloses all the features regarding claim 4 as indicated above. Kinzer does not explicitly disclose wherein the current flow control circuit includes a first path having a first impedance element coupled in series with a first unidirectional current conductor oriented to allow current to flow to the first gate terminal and a second path having a second impedance element coupled in series with a second unidirectional current conductor oriented to allow current to flow from the first gate terminal.
However, Leong discloses [fig. 5a and 5b] wherein the current flow control circuit includes a first path [first dotted pathways through CGD] having a first impedance element [CGD] coupled in series with a first current conductor [Lr conducting current related to CGD pathway] oriented to allow current to flow to the first gate terminal [current ILR shown in fig. 5b positive between t0 and t1] and a second path [first second pathways through CGS] having a second impedance element [CGS] coupled in series with a second current conductor [Lr conducting current related to CGS pathway] oriented to allow current to flow from the first gate terminal [current ILR shown in fig. 5b negative between t3 and t4]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Leong to include the current flow control circuitry oriented to allow current to flow to and from the first gate terminal as taught by Leong to improve power consumption in a switching circuit. Kinzer in view of Leong does not explicitly disclose the first path being in series with a first unidirectional current conductor and the second path being in series with a second unidirectional current conductor.
However, Vos discloses [fig 3] the first path being in series with a first unidirectional current conductor [top right diode in 24 being in a first current pathway] and the second path being in series with a second unidirectional current conductor [top left diode in 24 being in a second current pathway. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kinzer in view of Leong to include the first and second unidirectional current conductors as taught by Vos to improve current detection and power consumption in a switching circuit.
Regarding claim 14, Kinzer discloses all the features regarding claim 13 as indicated above. Kinzer does not explicitly disclose wherein the current flow control circuit includes a first path having a first impedance element coupled in series with a first unidirectional current conductor oriented to allow current to flow to the first gate terminal and a second path having a second impedance element coupled in series with a second unidirectional current conductor oriented to allow current to flow from the first gate terminal.
However, Leong discloses [fig. 5a and 5b] wherein the current flow control circuit includes a first path [first dotted pathways through CGD] having a first impedance element [CGD] coupled in series with a first current conductor [Lr conducting current related to CGD pathway] oriented to allow current to flow to the first gate terminal [current ILR shown in fig. 5b positive between t0 and t1] and a second path [first second pathways through CGS] having a second impedance element [CGS] coupled in series with a second current conductor [Lr conducting current related to CGS pathway] oriented to allow current to flow from the first gate terminal [current ILR shown in fig. 5b negative between t3 and t4]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Leong to include the current flow control circuitry oriented to allow current to flow to and from the first gate terminal as taught by Leong to improve power consumption in a switching circuit. Kinzer in view of Leong does not explicitly disclose the first path being in series with a first unidirectional current conductor and the second path being in series with a second unidirectional current conductor.
However, Vos discloses [fig 3] the first path being in series with a first unidirectional current conductor [top right diode in 24 being in a first current pathway] and the second path being in series with a second unidirectional current conductor [top left diode in 24 being in a second current pathway. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kinzer in view of Leong to include the first and second unidirectional current conductors as taught by Vos to improve current detection and power consumption in a switching circuit.
Claims 16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer in view of Leong.
Regarding claim 16, Kinzer discloses a circuit [fig. 6] comprising: a transistor [110] including a gate terminal, a source terminal and a drain terminal; and a gate driver circuit including: a pull-down transistor [610] coupled to the gate terminal [as shown]. An input terminal [Drain shown in fig. 7] arranged to receive an input signal [inherent] and generate a corresponding output signal at an output terminal coupled to the gate terminal [725, 750 and 730 outputting signal on gate of 110]. Kinzer does not explicitly disclose wherein the gate driver circuit stores energy harvested directly from the input signal and uses the stored harvested energy to change a conductive state of the pull- down transistor.
However, Leong disclose [fig. 5a] wherein the gate driver circuit [MS1 and MS2 and related circuity] stores energy harvested directly from the input signal [VCC, col 4 lines 6-13] and uses the stored harvested energy [col 2 lines 41-44] to change a conductive state of the pull-down transistor [MS2 controlled via 520]. Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date to modify the invention as described by Kinzer to include the storage of harvested energy from an input signal in order to change the conductive state of the pull down transistor as taught by Leong to improve power consumption in a switching circuit.
Regarding claim 20, Kinzer in view of Leong discloses further wherein the transistor is disposed in a gallium nitride (GaN)-based die [Kinzer, col 6 lines 21-41] and the gate driver circuit is disposed in a silicon-based [Kinzer, col 6 lines 21-41], and wherein the GaN-based die and the silicon-based die are co-packaged in a unitary semiconductor package [Kinzer, as shown in fig. 8].
Claims 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kinzer in view of Leong further in view of Teggatz et al. (US 20120293021 A1 and Teggatz hereinafter.).
Regarding claim 17, Kinzer in view of Leong discloses all the features regarding claim 16 as indicated above. Kinzer in view of Leong does not explicitly disclose wherein the gate driver circuit uses the stored energy to operate an over-temperature protection circuit.
However, Teggatz discloses that it was known in the art to provide a temperature sensor within an energy harvesting and gate driving switching system as shown in fig. 2 and para. 25. It would have been obvious to one having ordinary skill in the art before the effective filing date to provide the gate driver circuit uses the stored energy to operate an over-temperature protection circuit with the system of a temperature sensor within an energy harvesting and gate driving switching system of Teggatz, in order to improve usability in an energy harvesting circuit. See In re Preda, 159 USPQ 342 (CCPA, 1968).
Regarding claim 18, Kinzer in view of Leong discloses the claimed invention as indicated above. Kinzer in view of Leong does not explicitly disclose wherein the gate driver circuit further comprises an over-temperature protection circuit.
However, Teggatz discloses that it was known in the art to provide a temperature sensor within an energy harvesting and gate driving switching system as shown in fig. 2 and para. 25. It would have been obvious to one having ordinary skill in the art before the effective filing date to provide the gate driver circuit further comprises an over-temperature protection circuit with the system of a temperature sensor within an energy harvesting and gate driving switching system of Teggatz, in order to improve usability in an energy harvesting circuit. See In re Preda, 159 USPQ 342 (CCPA, 1968).
Regarding claim 19, Kinzer in view of Leong further in view of Teggatz discloses further wherein the gate driver circuit uses the stored energy to further operate the over-temperature protection circuit [para. 25 of Teggatz and col 2 lines 41-44 of Leong].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's
disclosure, Dietrich (US 10931277) is cited to teach energy harvesting using gate driving circuitry.
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/JAMES G YEAMAN/Examiner, Art Unit 2836
/TAELOR KIM/Supervisory Patent Examiner, Art Unit 2836
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