Prosecution Insights
Last updated: October 02, 2026
Application No. 18/893,873

METHODS, APPARATUSES, INTEGRATED CIRCUITS, AND PRINTED CIRCUIT BOARDS FOR POWER CONVERSION WITH REDUCED PARASITICS

Non-Final OA §102§103
Filed
Sep 23, 2024
Priority
Mar 21, 2022 — provisional 63/321,930 +1 more
Examiner
TRAN, BINH BACH THANH
Art Unit
Tech Center
Assignee
Murata Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
574 granted / 710 resolved
+20.8% vs TC avg
Moderate +12% lift
Without
With
+12.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
16 currently pending
Career history
724
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
29.3%
-10.7% vs TC avg
§112
9.2%
-30.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 – 3, 6, 7, 18, 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Palm (US 20190081562). Regarding claim 1, Palm discloses a printed circuit board (PCB, Fig. 3B) for power conversion, the PCB comprising: a plurality of integrated circuits (the package 102 including the circuitry M1, M2 and drive circuit 100 that have integrated circuit; paragraph 20), wherein each integrated circuit of the plurality of integrated circuits comprises buck converter circuitry (paragraph 20); and a plurality of inductors (the inductor L in module 104), wherein each inductor of the plurality of inductors is coupled to a respective integrated circuit of the plurality of integrated circuits (the plurality of inductor module coupled to the integrated circuit packages; Fig. 2). Regarding claim 2, Palm discloses the claimed invention as set forth in claim 1. Palm further suggests each integrated circuit of the plurality of integrated circuits is coupled to a respective inductor of the plurality of inductors by a corresponding terminal (solder joints 202, Fig. 2). Regarding claim 3, Palm discloses the claimed invention as set forth in claim 2. Palm further suggests each corresponding terminal is positioned on a common side (the side between the inductor and the integrated circuit package 102) of each integrated circuit of the plurality of integrated circuits. Regarding claim 6, Palm discloses the claimed invention as set forth in claim 1. Palm further suggests the plurality of inductors (104, Fig. 2) are adjacent to each other on a common side of the plurality of integrated circuits (102). Regarding claim 7, Palm discloses the claimed invention as set forth in claim 1. Palm further suggests the plurality of integrated circuits are adjacent to each other (Fig. 2). Regarding claim 18, Palm discloses a printed circuit board (PCB; Fig. 3B) for power conversion, the PCB comprising: an integrated circuit (IC package 102) comprising buck converter circuitry (paragraph 20); and an inductor (inductor module 104) coupled to the integrated circuit (102). Regarding claim 20, Palm discloses an apparatus (a power semiconductor system) comprising the PCB (Fig. 3B) of claim 18. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 10, 11, 12, 15, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Palm (US 20190081562), in view of Sturcken (US 20160036330). Regarding claim 10, Palm discloses a printed circuit board (PCB) for power conversion, the PCB comprising: a plurality of integrated circuits (the plurality of integrated circuit package 102; Fig. 2) comprising a first integrated circuit (package 102) and a second integrated circuit (another integrated circuit package 102), wherein the first integrated circuit and the second integrated circuit each comprises buck converter circuitry (paragraph 20), and wherein the first integrated circuit and the second integrated circuit are positioned adjacent to each other (Fig. 2); a first inductor (inductor package 104) coupled to the first integrated circuit; and a third inductor (another inductor coupled to another IC package 102) coupled to the second integrated circuit. Palm does not explicitly disclose and a second inductor each coupled to the first integrated circuit and a fourth inductor each coupled to the second integrated circuit. Sturcken suggests two inductors (660, 660’) coupled to one IC package (610, Fig. 6). It would have been obvious to one having skill in the art at the effective filing date of the invention to increase number of components as needed in order to improve the function of the circuitry. Regarding claim 11, Palm, in view of Sturcken, discloses the claimed invention as set forth in claim 10. Sturcken further suggests the first integrated circuit is coupled to the first inductor by a first corresponding terminal (the connection point between 660 and the package 610) and the first integrated circuit is coupled to the second inductor by a second corresponding terminal (the connection point between 660’ and the package 610); and wherein the second integrated circuit is coupled to the third inductor by a third corresponding terminal and the second integrated circuit is coupled to the fourth inductor by a fourth corresponding terminal (the duplication of IC and inductor package as suggested by Palm). Regarding claim 12, Palm, in view of Sturcken, discloses the claimed invention as set forth in claim 10. Palm further suggests each of the first terminal, the second terminal, the third terminal, and the fourth terminal are positioned on a common side (the side between the IC package and the inductor module) of each integrated circuit of the plurality of integrated circuits (Fig. 2). Regarding claim 15, Palm, in view of Sturcken, discloses the claimed invention as set forth in claim 10. Palm further suggests the first inductor, the second inductor, the third inductor, and the fourth inductor are adjacent to each other on a common side of the first integrated circuit and the second integrated circuit (all the inductors are adjacent to the side between the IC package and the inductor module). Regarding claim 19, Palm discloses the claimed invention as set forth in claim 18. Palm does not explicitly disclose the inductor comprises a plurality of inductors (104; Fig. 2) coupled to the integrated circuit, the integrated circuit is coupled to each inductor of the plurality of inductors by a corresponding terminal, and wherein each corresponding terminal is positioned on a common side of the integrated circuit. Palm suggests a plurality of inductors (104) coupled to a plurality of IC packages (102, Fig. 2) at a common side. Sturcken suggests two inductors (660, 660’) coupled to one IC package (610, Fig. 6). It would have been obvious to one having skill in the art at the effective filing date of the invention to increase number of components as needed in order to improve the function of the circuitry. Allowable Subject Matter Claims 4, 5, 8, 9, 13, 14, 16, 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Reasons for Allowance The following is an examiner’s statement of reasons for allowance: Regarding claim 4, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 1 and 2, a combination of limitations that a plurality of ground terminals adjacent to each other on a common side of the plurality of integrated circuits, wherein the plurality of ground terminals are further adjacent to the plurality of inductors. None of the reference art of record discloses or renders obvious such a combination. Regarding claim 8, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that each integrated circuit of the plurality of integrated circuits is coupled to a corresponding charge pump. None of the reference art of record discloses or renders obvious such a combination. Regarding claim 13, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claims 10 and 11, a combination of limitations that a first ground terminal is coupled to the first terminal, a second ground terminal is coupled to the second terminal, a third ground terminal is coupled to the third terminal, and a fourth ground terminal is coupled to the fourth terminal. None of the reference art of record discloses or renders obvious such a combination. Regarding claim 16, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 10, a combination of limitations that the first integrated circuit is coupled to a first charge pump and the second integrated circuit is coupled to a second charge pump. None of the reference art of record discloses or renders obvious such a combination. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ladret (US 20150162831) discloses an IC package coupled to inductors, Fig. 4. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BINH B TRAN/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 23, 2024
Application Filed
Sep 09, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
93%
With Interview (+12.1%)
2y 5m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

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