Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 4, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "wherein magnetic field sensor…" in ll. 1-2, which was previously disclosed in claim 11. The repeated recitation of “magnetic field sensor…”, introduces indefinites, for this limitation in the claim. For examination purposes, the examiner interprets “wherein magnetic field sensor…”, to refer to the same previously disclosed limitation, “a magnetic field sensor” in claim 11.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 10, & 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Khoury (US 2023/0308111 A1, Pub. Date Sep. 28, 2023, hereinafter, Khoury), in view of Rud et al. (EP 2417466 B1, Pub. Date Feb. 21, 2018, hereinafter, Rud).
Regarding independent claim 1, Khoury, teaches:
An analog-to-digital conversion (ADC) circuit for a sensor signal, comprising (Fig. 1; [Abstract] & [0026]):
an input interface configured to receive an analog sensor signal (Fig. 2; [Abstract], [0026], [0030], & [0041]: summer 210 interpreted as the input interface);
an analog-to-digital converter configured to digitize the analog sensor signal to obtain samples of a digital sensor signal ([0026]-[0027], [0030], [0033]-[0034], & [0041]: digitizes the sensor signal into digital samples);
a digital filter configured to average a number of samples of the digital sensor signal to obtain an averaged sensor signal ([0041]-[0043]);
an output interface configured to output the averaged sensor signal ([0040]-[0043] & [0049]-[0050]: summer 380 outputs the averaged sensor signal).
Khoury, is silent in regard to:
a processor configured to adjust the number of averaged samples to obtain the averaged sensor signal based on one or more characteristics of the analog sensor signal or the digital sensor signal; and
However, Rud, further teaches:
a processor configured to adjust the number of averaged samples to obtain the averaged sensor signal based on one or more characteristics of the analog sensor signal or the digital sensor signal (Fig. 1; [0010]-[0013], [0015], [0022]-[0024], & [0027]: teaches a microprocessor configured to evaluate a characteristic of the sensor signal (amplitude crossing a threshold, or noise frequency) and based on this characteristic, the processor adjust the decimation period (adjusting the number of averaged samples) of the sigma-delta decimation period); and
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the dynamic decimation period adjustment taught by Rud into the decimation filters of Khoury, according to known methods. The motivation to do so would be to allow the ADC circuit dynamically optimize its decimation filtering response to changing sensor signal noise amplitudes, providing maximum noise reduction when noise is high. The incorporation of Rud’s dynamic adjustment logic into Khoury’s systems would have been a simple optimization of a known device. The optimization provides maximum noise reduction (via averaging) when signal noise is high, while maintaining faster update rates and lowering overall power consumption when the signal noise is low. Implementing this optimization would require no undue experimentation, as the underlying hardware architecture in Khoury is capable of supporting it, yielding expected predictable results (KSR).
Regarding dependent claim 2, Khoury, teaches:
The ADC circuit of claim 1 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the one or more characteristics of the analog sensor signal or the digital sensor signal comprise a signal strength and/or a signal dynamic of the analog sensor signal or the digital sensor signal.
However, Rud, further teaches:
wherein the one or more characteristics of the analog sensor signal or the digital sensor signal comprise a signal strength and/or a signal dynamic of the analog sensor signal or the digital sensor signal ([0001], [0010], [0013]-[0014], [0019], [0022], [0024]-[0027], [Claim 3], [Claim 4], [Claim 5], [Claim 6], [Claim 7], [Claim 8], & [Claim 10]: teaches that the one or more characteristics monitored to adjust the decimation filter is the amplitude of the sensor signal’s noise component, where amplitude constitutes signal strength and/or signal dynamic).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the incorporated processor of Khoury/Rud to use signal strength (amplitude) as the characteristic for adjusting the decimation period, according to known methods. A POSITA would recognize that signal amplitude is a direct measurement of signal strength and signal dynamics. This optimization applies Rud’s amplitude-based trigger to the combined system to mitigate high-strength line noise, yielding expected predictable results (KSR).
Regarding dependent claim 3, Khoury, teaches:
The ADC circuit of claim 1 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the processor is configured to determine a signal strength of the analog sensor signal or the digital sensor signal and to adjust the number of averaged samples based on the signal strength.
However, Rud, further teaches:
wherein the processor is configured to determine a signal strength of the analog sensor signal or the digital sensor signal ([0010], [0014], [0018]-[0019], [0021]-[0022], & [Claim 1]: compares the analog signal to a reference voltage threshold to determine if the amplitude crosses the threshold, therefore, determining the signal strength of the analog sensor signal) and to adjust the number of averaged samples based on the signal strength ([0010], [0013], [0022], [0024], & [0027]: teaches that when the amplitude (signal strength) reaches a certain level, the microprocessor adjusts the decimation period of the sigma-delta filter. Adjusting the decimation period constitutes adjusting the number of averaged samples, therefore the adjustment is based on the signal strength).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the processor in the combined Khoury/Rud system to determine signal strength and adjust the decimation samples based on that strength, according to known methods. The motivation for this substitution and optimization is to allow the system to continuously monitor real-time noise severity and dynamically trigger filtering when the noise strength is high, conserving power and maximizing update rates when signal strength dynamics allow this, as predictably taught by Rud, yielding expected predictable results (KSR).
Regarding dependent claim 10, Khoury, teaches:
The ADC circuit of claim 1 (Fig. 1; [Abstract], [0007], [0010]-[0011], [0026]-[0027], [Claim 10], [Claim 11], [Claim 18], & [Claim 19]), wherein the analog-to-digital converter comprises a sigma-delta ADC ([0007], [0010]-[0011], [0027], [0034], [Claim 10], [Claim 11], [Claim 18], & [Claim 19]).
Regarding independent claim 13, Khoury, teaches:
A method for analog-to-digital conversion of a sensor signal, the method comprising (Fig. 1; [Abstract] & [0026]):
receiving an analog sensor signal (Fig. 2; [Abstract], [0026], [0030], & [0041]);
digitizing the analog sensor signal to obtain samples of a digital sensor signal ([0026]-[0027], [0030], [0033]-[0034], & [0041]: teaches the step of digitizing the analog sensor signal into discrete digital samples);
outputting the averaged sensor signal ([0040]-[0043] & [0049]-[0050]: teaches the step of outputting the resulting filtered/averaged digital signal for downstream processing).
Khoury, is silent in regard to:
averaging a number of samples of the digital sensor signal to obtain an averaged sensor signal;
adjusting the number of averaged samples to obtain the averaged sensor signal based on one or more characteristics of the analog sensor signal or the digital sensor signal; and
However, Khoury, in combination with Rud, further teach:
averaging a number of samples of the digital sensor signal to obtain an averaged sensor signal (Khoury: [0041]-[0043]: teaches utilizing FIR decimation filters to process the digitized samples; Rud: [0024]-[0028]: teaches the step of applying a sigma-delta decimation filter, which operates by averaging a specific number of discrete samples over a decimation period to produce a lower-rate, higher-resolution averaged output signal);
Khoury discloses a method for analog-to-digital conversion of a sensor signal, comprising receiving an analog signal, digitizing it into digital samples, applying digital decimation (averaging) filters, and outputting the result. Rud teaches a method for operating a sensor ADC wherein the decimation period of a sigma-delta decimation filter (the number of averaged samples) is adjusted based on a measured characteristic of the signal, the line noise frequency period. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the dynamic decimation adjustment steps of Rud into the ADC method of Khoury. The motivation to do so is to dynamically optimize the digital filtering process to reject varying environmental noise while conserving power and bandwidth, yielding a predictable improvement (KSR) to the digital signal processing method.
However, Rud, further teaches:
adjusting the number of averaged samples to obtain the averaged sensor signal based on one or more characteristics of the analog sensor signal or the digital sensor signal (Fig. 1; [0010]-[0013], [0015], [0022]-[0024], & [0027]: teaches the step of dynamically adjusting the decimation period (i.e., adjusting the number of averaged samples in the digital filter) based on a monitored characteristic of the signal, the frequency/period P of the noise); and
Khoury discloses a method for analog-to-digital conversion of a sensor signal, comprising receiving an analog signal, digitizing it into digital samples, applying digital decimation (averaging) filters, and outputting the result. Rud teaches a method for operating a sensor ADC wherein the decimation period of a sigma-delta decimation filter (the number of averaged samples) is adjusted based on a measured characteristic of the signal, the line noise frequency period. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the dynamic decimation adjustment steps of Rud into the ADC method of Khoury, according to known methods. The motivation to do so is to dynamically optimize its digital filtering process to reject varying environmental, while conserving power and bandwidth, yielding a predictable improvement to the digital signal processing method. The incorporation of Rud’s dynamic adjustment logic into Khoury’s systems would have been a simple optimization of a known device. The optimization provides maximum noise reduction (via averaging) when signal noise is high, while maintaining faster update rates and lowering overall power consumption when the signal noise is low. Implementing this optimization would require no undue experimentation, as the underlying hardware architecture in Khoury is capable of supporting it, yielding expected predictable results (KSR).
Regarding dependent claim 14, Khoury, teaches:
The method of claim 13 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the one or more characteristics of the analog sensor signal or the digital sensor signal comprise a signal strength and/or a signal dynamic of the analog sensor signal or the digital sensor signal.
However, Rud, further teaches:
wherein the one or more characteristics of the analog sensor signal or the digital sensor signal comprise a signal strength ([0001], [0010], [0013]-[0014], [0019], [0022], [0024]-[0027], [Claim 3], [Claim 4], [Claim 5], [Claim 6], [Claim 7], [Claim 8], & [Claim 10]: teaches measuring the amplitude of the sensor signal (constitutes the signal strength) to determine when to trigger the adjustment of the A/D converter’s decimation period) and/or a signal dynamic of the analog sensor signal or the digital sensor signal ([0001], [0010], [0013]-[0014], [0019], [0022], [0024]-[0027], [Claim 3], [Claim 4], [Claim 5], [Claim 6], [Claim 7], [Claim 8], & [Claim 10]: teaches evaluating the frequency period P of the signal. Frequency and period are fundamental measures of a signal’s rate of change (signal dynamic)).
The method of Khoury is modified by Rud to adjust the number of averaged samples (decimation period) based on a signal characteristic. Rud teaches that this characteristic comprises both a signal strength, by evaluating the noise amplitude against a threshold, and a signal dynamic, by measuring the line noise frequency period P. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the method of Khoury to monitor the specific characteristics (amplitude and frequency), as taught by Rud, to use signal strength (amplitude) as the characteristic for adjusting the decimation period, according to known methods. A POSITA would recognize that signal amplitude is a direct measurement of signal strength and signal dynamics. This optimization applies Rud’s amplitude-based trigger to the combined system to mitigate high-strength line noise. Doing so predictably allows the digital signal processing to adapt to the specific magnitude and dynamics of environmental interference, optimizing power and filter resolution, and yielding expected predictable results (KSR).
Regarding dependent claim 15, Khoury, teaches:
The method of claim 13 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, is silent in regard to:
determining a signal strength of the analog sensor signal or the digital sensor signal, wherein the number of averaged samples is adjusted based on the signal strength.
However, Rud, further teaches:
determining a signal strength of the analog sensor signal or the digital sensor signal (Fig. 2; [0010], [0014], [0018]-[0019], [0021]-[0022], & [Claim 1]: teaches the method step of determining the signal strength by monitoring the amplitude of the sensor signal to determine when it exceeds a defined threshold), wherein the number of averaged samples is adjusted based on the signal strength ([0010], [0013], [0022], [0024], & [0027]: teaches the step of adjusting the decimation period (the number of averaged samples) in response to the monitored amplitude/signal strength of the noise crossing the established thresholds).
The method of Khoury is modified by Rud to adjust the decimation period (number of averaged samples) of the digital filter based on a signal characteristic. Rud teaches the step of determining the signal strength by measuring the amplitude of the sensor signal against a noise amplitude threshold. When the amplitude (signal strength) dictates a change in the noise profile, Rud, further teaches adjusting the decimation period of the sigma-delta filter accordingly. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the amplitude-monitoring and decimation-adjustment step into the ADC method of Khoury, according to known methods. The motivation to do so is to dynamically optimize the digital filtering process so that the system provides averaging when the signal strength of the noise requires it, conserving power and maximizing signal resolution, as predictably taught by Rud, yielding expected predictable results (KSR).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Khoury, in view of Rud, and further in view of Krah et al (US 2011/0061947 A1, Pub. Date Mar. 17, 2011, hereinafter, Krah).
Regarding dependent claim 9, Khoury, teaches:
The ADC circuit of claim 1 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, in combination with Rud, are silent in regard to:
a selector configured to select the one or more characteristics of the analog sensor signal or the digital sensor signal based on which to adjust the number of averaged samples.
However, Krah, further teaches:
a selector configured to select the one or more characteristics of the analog sensor signal or the digital sensor signal based on which to adjust the number of averaged samples ([0090]-[0092] & [0094]-[0095]: teaches that the power management logic 145 (selector) can be configured to select which characteristic to use for the adjusted integration time (equates to the number of averaged samples), choosing to base the adjustment on detected noise (amplitude) or as an alternative, choosing to base it on phase increment (frequency/signal dynamic)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the multi-parameter selection logic taught by Krah into the Khoury/Rud ADC system, according to known methods. The motivation for a POSITA to implement this selector would be to provide a flexible, configurable ADC architecture. By allowing the system to select which characteristic drives the decimation adjustment( e.g., allowing the system to toggle between frequency-based tracking and amplitude-based tracking depending on the specific operational mode or the specific hardware device being utilized), the ADC can predictably optimize its power consumption and noise rejection across a wider variety of environmental interference scenarios. The incorporation of Krah’s selector logic into the base system constitutes the application of a known technique to a known device to yield expected predictable results (KSR).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Khoury, in view of Rud, and further in view of Trifonov et al. (US 2024/0337708 A1, Fil. Date Jul. 31, 2023, hereinafter, Trifonov).
Regarding dependent claim 11, Khoury, teaches:
The ADC circuit of claim 1 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, in combination with Rud, are silent in regard to:
a magnetic field sensor coupled to the input interface to provide an analog magnetic field sensor signal.
However, Trifonov, further teaches:
a magnetic field sensor coupled to the input interface to provide an analog magnetic field sensor signal (Figs. 1B, 3, & 4A; [Abstract], [0003], [0017], [0023], [0025], [0043]-[0044], & [0050]: teaches utilizing a magnetic field sensor (Hall effect sensor) to sense a magnetic field and generate an analog output voltage. Further teaches coupling the analog magnetic field signal to the input interface of an ADC (e.g., ADC 301/406)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to substitute the audio sensor of Khoury with a magnetic field sensor as taught by Trifonov, coupling the magnetic field sensor to the input interface of the Khoury/Rud ADC circuit, according to known methods. The motivation for a POSITA to perform this combination would be to leverage the dynamically adjustable sigma-delta ADC architecture of Khoury and Rud to digitize magnetic field measurements. A POSITA would recognize that magnetic field sensors suffer from environmental noise, as disclosed by Trifonov, making them candidates for the dynamic noise-tracking decimation filters taught by the Khoury/Rud combination to ensure high-precision, low-noise digital magnetic field readings. This is a substitution of one known sensor type for another to yield the expected predictable result (KSR) of digitizing its analog output.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Khoury, in view of Rud, in view of Trifonov, and further in view of Kolen (US 2007/0219744 A1, Pub. Date Sep. 20, 2007, hereinafter, Kolen).
Regarding dependent claim 12, Khoury, teaches:
The ADC circuit of claim 11 (Fig. 1; [Abstract] & [0026]),
Khoury, in combination with Rud, are silent in regard to:
wherein magnetic field sensor comprises a 3D Hall sensor.
However, Trifonov, in combination with Kolen, further teach:
wherein magnetic field sensor (Trifonov: [Abstract], [0003], [0017], [0023], [0025], [0043]-[0044], & [0050]) comprises a 3D Hall sensor (Kolen: [Abstract], [0020]-[0021], [0029], [0045], [0063], [0076], [0079], [0085], [0127], [0179], [0183], [0191], [0219], [Claim 4], [Claim 5], [Claim 6], [Claim 10], [Claim 11], [Claim 12], & [Claim 13]: a tri-axial magnetometer is the industry-standard terminology used for a 3-Dimensional (3D) magnetic field sensor).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the Hall effect magnetic field sensor of Trifonov as a tri-axial (3D) magnetometer, as taught by Kolen, according to known methods. The motivation for a POSITA to perform this combination would be to allow the ADC circuit to capture spatial magnetic data across all three Cartesian axes (X, Y, and Z) rather than a single plane. Applying this 3D spatial data to the dynamically adjustable sigma-delta ADC filters of the Khoury/Rud combination predictably enables precise, multi-directional magnetic field tracking while dynamically rejecting environmental noise on any given axis. Due to Hall sensors being a standard solid-state implementation of magnetometers, adapting Trifonov’s Hall sensor into a 3D/tri-axial configuration is a substitution of one known magnetic sensor architecture for another to yield expected predictable results (KSR).
Claims 4-8 & 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Khoury, in view of Rud, and further in view of Ruha et al. (US 2003/0067404 A1, Pub. Date Apr. 10, 2003, hereinafter, Ruha).
Regarding dependent claim 4, Khoury, teaches:
The ADC circuit of claim 3 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the processor is configured to reduce the number of averaged samples based on an increase in the signal strength and to increase the number of averaged samples based on a decrease in the signal strength.
However, Rud, in combination with Ruha, further teach:
wherein the processor is configured to reduce the number of averaged samples based on an increase in the signal strength (Rud: Figs. 4 & 6; [0015], [0021]-[0022] & [0024]-[0028]: higher amplitude (threshold crossing) triggers slower sample rate (fewer samples per time window), Fig. 4 time period 94, Fig. 6 steps 204-206; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: enables the dynamic programming of the OSR (averaging length)) and to increase the number of averaged samples based on a decrease in the signal strength (Rud: Figs. 4 & 6; [0021]-[0022] & [0024]-[0028]: lower amplitude (no threshold crossing) triggers faster sample rate (more samples per time window), further teaching that the decimation period (averaging length) is specific variable controlled for adaptive noise rejection, Fig. 4 time period 92, Fig. 6 step 206; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: teaches that the OSR is dynamically programmable).
Ruha provides the teaching that a programmable signal converter core, a sigma-delta modulator, has a dynamically programmable oversampling ratio (OSR). Rud teaches that the decimation period (the number of averaged samples) is the specific parameter adjusted to control filter performance relative to signal conditions. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the programmable processor of the ADC to execute a control loop that increases the number of averaged samples when the signal strength is low (to maximize SNR) and decreases the number of averaged samples when the signal strength is high (to optimize power consumption), as this bi-directional adaptive behavior is the standard, predictable implementation of a power-aware sigma-delta ADC core, as enabled by the teachings of Ruha. Substituting Khoury’s quantizer for a conventional quantizer (adaptive ADC of Rud/Ruha to further reduce power) is a predictable variation. The combination would reduce power while retaining adaptive noise rejection and there is a finite number of solutions to the power-noise trade-off, making the combination obvious, and yielding expected predictable results (KSR).
Regarding dependent claim 5, Khoury, teaches:
The ADC circuit of claim 3 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the processor is configured to perform a comparison of the signal strength and one or more predefined threshold values and to select the number of averaged samples based on the comparison.
However, Rud, further teaches:
wherein the processor is configured to perform a comparison of the signal strength and one or more predefined threshold values (Fig. 2; [0010], [0014]-[0015], [0018]-[0019], [0024]-[0028], & [Claim 1]: teaches a comparator (part of the processor/controller logic) comparing the sensor signal strength (amplitude) to a predefined threshold (Vref/noise amplitude threshold))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ADC circuit of Khoury by implementing the dynamic decimation filtering methodology taught by Rud, according to known methods. Rud teaches a microprocessor-controlled systems that performs the comparison between the inputs signal’s amplitude (signal strength) and a predefined noise amplitude threshold. This modification represents the application of a known technique (dynamic decimation adjustment) to a known device (Khoury’s sensor ADC) to yield the predictable result: improved signal-to-noise ratio (SNR) in the presence of time-varying environmental interference. The combination predictably allows Khoury’s system to adaptively balance its digital filtering intensity against power consumption and signal bandwidth. When high-resolution filtering is required, the decimation period can be increased; when noise is low, the decimation period can be decreased. This is a known technique for optimizing power consumption and noise performance in ADC signal processing chains, yielding expected predictable results (KSR).
However, Rud, in combination with Ruha, further teach:
and to select the number of averaged samples based on the comparison (Rud: [0024]-[0028]: teaches that the decimation period (the number of averaged samples) is adjusted as a function of the signal dynamics; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: provides the hardware teaching for a programmable signal converter core configured to dynamically select the conversion parameters (OSR/averaging) based on the operational state determined by the comparison).
Rud teaches that the hardware configuration for performing a comparison of a sensor signal’s strength against predefined thresholds and using this to trigger an adjustment of the decimation period (the number of averaged samples). Ruha provides the hardware teaching for a programmable signal converter core that is configured to dynamically select/program conversion parameters, such as the oversampling ratio (the number of averaged samples), based on the system’s operational requirements as determined by signal monitoring. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the ADC processor of Khoury and Rud such that it includes the comparison logic of Rud and the programmable selection logic of Ruha, according to known methods. This combination represents the standard hardware architecture for an adaptive-bandwidth sigma-delta ADC. Based on the outcome of this comparison, the system dynamically selects and adjusts the decimation period (the number of averaged samples) within the sigma-delta decimation filter. This is a known technique for optimizing power consumption and noise performance in ADC signal processing chains, yielding expected predictable results (KSR).
Regarding dependent claim 6, Khoury, teaches:
The ADC circuit of claim 1 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the processor is configured to determine a signal dynamic of the analog sensor signal or the digital sensor signal and to adjust the number of averaged samples used to obtain the averaged sensor signal based on the signal dynamic.
However, Rud, further teaches:
wherein the processor is configured to determine a signal dynamic of the analog sensor signal or the digital sensor signal (Fig. 3; [0014]-[0015], [0018]-[0019], [0021]-[0022], [0024], & [0027]-[0028]: frequency and period (P) of a signal constitute the metrics of a signal dynamic)
Rud teaches that an A/D converter’s decimation period, which governs the number of averaged samples, can be dynamically adjusted as a function of measured signal characteristics, such as the line noise frequency period, where a microprocessor determines the frequency/period (a signal dynamic) of line noise detected in the sensor signal. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ADC circuit of Khoury by implementing the dynamic decimation filtering technology taught by Rud, according to known methods. This modification represents the application of a known technique (dynamic decimation adjustment) to a known device (Khoury’s sensor ADC) to yield a predictable result: improved signal-to-noise ratio (SNR) in the presence of time-varying environmental interference. The combination predictably allows Khoury’s system to adaptively balance its digital filtering intensity against power consumption and signal bandwidth. When high-resolution filtering is required, the decimation period can be increased; when noise is low, the decimation period can be decreased. To dynamically tune the number of averaged samples (the decimation rate) in response to the specific dynamic characteristics of the sensor environment, optimizing the system’s noise rejection, and yield expected predictable results (KSR) as predictably.
However, Rud, in combination with Ruha, further teach:
and to adjust the number of averaged samples used to obtain the averaged sensor signal based on the signal dynamic (Rud: [0024]-[0028]: teaches the logic for adjusting the decimation period (the actual number of averaged samples) as a function of the calculated signal dynamic (the line noise frequency period P); Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: enables the hardware (programmable core) to adjust the OSR/averaging count).
Rud provides the enabling hardware teaching for a controller that determines a signal dynamic (the frequency period P) and adjusts the decimation period (the number of averaged samples of the sigma-delta filter) in response. Ruha confirms that it is well-known to implement such dynamic adjustments in a sigma-delta ADC using a programmable signal converter core to vary the parameters such as the oversampling ratio as a function of operational conditions. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the ADC processor of Khoury and Rud, according to known methods. Such that it includes the dynamic analysis logic of Rud and the programmable adjustment logic of Ruha, as this combination represents the standard hardware architecture for an adaptive-bandwidth sigma-delta ADC. Further, to dynamically tune the number of averaged samples (the decimation rate) in response to the specific dynamic characteristics of the sensor environment, optimizing the system’s noise rejection, yielding expected predictable results (KSR).
Regarding dependent claim 7, Khoury, teaches:
The ADC circuit of claim 6 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the processor is configured to reduce the number of averaged samples based on an increase in the signal dynamic and to increase the number of averaged samples based on a decrease in the signal dynamic.
However, Rud, in combination with Ruha, further teach:
wherein the processor is configured to reduce the number of averaged samples based on an increase in the signal dynamic (Rud: Fig. 3; [0014]-[0015], [0018]-[0019], [0021]-[0022], [0024], & [0027]-[0028]: monitors the signal dynamic (frequency/period P), when the dynamic behavior (e.g., frequency) indicates the need for a change, the processors reduces the decimation period to properly track the signal dynamic; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: provides the enabling hardware for a programmable signal converter core that dynamically adjusts OSR (number of averaged samples)) and to increase the number of averaged samples based on a decrease in the signal dynamic (Rud: [0024]-[0028]: as the monitored frequency (signal dynamic) decreases, adjusts the decimation period (averaging) proportionally, increases the number of averaged samples; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]).
Rud provides the enabling hardware teaching for a controller that determines a signal dynamic (the frequency period P) and adjust the decimation period (the number of averaged samples) in response. Ruha confirms that it is well-known to implement such dynamic adjustments in a sigma-delta ADC using a programmable signal converter core to vary parameters such as the oversampling ratio as a function of operational conditions. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the ADC processor of Khoury and Rud, according to known methods. Such that it includes the dynamic analysis logic of Rud and the bi-directional programmable adjustment logic of Ruha. The motivation for a POSITA to perform this optimization would be to allow the ADC circuit to dynamically tune its filter response to match the changing frequency/dynamics of the environment. This combination represents the standard hardware architecture for an adaptive-bandwidth sigma-delta ADC capable of scaling filter length in both directions relative to signal dynamics. Further, a POSITA would recognize that reducing the number of averaged samples when the signal dynamic increases (higher frequency) prevents the loss of high-frequency signal information and minimizes latency. Conversely, increased the number of averaged samples when the signal dynamic decreases allows the system to filter out slow, steady-state noise, predictably maximizing the signal-to-noise ratio across varying operating states, yielding expected predictable results (KSR).
Regarding dependent claim 8, Khoury, teaches:
The ADC circuit of claim 6 (Fig. 1; [Abstract] & [0026]),
Khoury, is silent in regard to:
wherein the processor is configured to perform a comparison of the signal dynamic and one or more predefined threshold values and to select the number of averaged samples based on the comparison.
However, Rud, further teaches:
wherein the processor is configured to perform a comparison of the signal dynamic and one or more predefined threshold values ([0003]-[0004], [0010], [0014]-[0015], [0018]-[0019], [0021]-[0022], [0024], [0027]-[0028], [Claim 1], [Claim 4], & [Claim 7]: teaches the processor determining the signal dynamic (frequency/period P), describes comparing the amplitude to a predefined threshold to trigger adjustments, determining discrete hardware settings (e.g., decimation period) as a function of a measured dynamic (frequency) requires the process to compared the measured dynamic against predefined ranges or threshold values (e.g., determining if the frequency falls into 50Hz or 60Hz threshold))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ADC circuit of Khoury by implementing the dynamic decimation filtering methodology taught by Rud, according to known methods. This modification represents the application of a known technique (dynamic decimation adjustment) to a known device (Khoury’s sensor ADC) to yield a predictable result: improved signal-to-noise ratio (SNR) in the presence of time-varying environmental interference. The combination predictably allows Khoury’s system to adaptively balance its digital filtering intensity against power consumption and signal bandwidth. When high-resolution filtering is required, the decimation period can be increased; when noise is low, the decimation period can be decreased. In digital signal processing, mapping a measured continuous variable (e.g., frequency) to select a discrete hardware setting (e.g., a decimation rate) involves comparing the measured value to a lookup table of predefined thresholds or ranges. This combination represents the standard hardware architecture for an adaptive-bandwidth sigma-delta ADC, to achieve the predictable result of optimizing the decimation filter for the specific noise environment detected, yielding expected predictable results (KSR).
However, Rud, in combination with Ruha, further teach:
and to select the number of averaged samples based on the comparison (Rud: [0024]-[0028]: based on the evaluation of the signal dynamic (frequency period P), teaches selecting/adjusting the decimation period of the filter, which dictates the number of averaged samples, as a function of the detected signal dynamics; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: provides the enabling hardware teaching for a programmable signal converter core configured to dynamically select the conversion parameters (OSR/averaging) based on the operational state determined by the comparison).
Rud teaches the hardware configuration for performing a comparison of a signal dynamic (the frequency period P) against predefined thresholds and using this comparison to trigger an adjustment of the decimation period (the number of averaged samples). Ruha teaches the hardware for a programmable signal converter core that is configured to dynamically select/program conversion parameters, such as the oversampling ratio (the number of averaged samples), based on the operational requirements as determined by the comparison of the detected signal dynamics. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the ADC processor of Khoury and Rud such that it includes the comparison logic of Rud to select the decimation rate by comparing the measured signal dynamic (frequency) against one or more predefined threshold values, and the programmable selection logic of Ruha, according to known methods. In digital signal processing, mapping a measured continuous variable (e.g., frequency) to select a discrete hardware setting (e.g., a decimation rate) involves comparing the measured value to a lookup table of predefined thresholds or ranges. This combination represents the standard hardware architecture for an adaptive-bandwidth sigma-delta ADC, to achieve the predictable result of optimizing the decimation filter for the specific noise environment detected, yielding expected predictable results (KSR).
Regarding dependent claim 16, Khoury, teaches:
The method of claim 15 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, is silent in regard to:
reducing the number of averaged samples based on an increase in the signal strength of the analog sensor signal or the digital sensor signal.
However, Rud, in combination with Ruha, further teach:
reducing the number of averaged samples based on an increase in the signal strength of the analog sensor signal or the digital sensor signal (Rud: [0015], [0021]-[0022] & [0024]-[0028]; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: teaches that the OSR of a sigma-delta modulator is dynamically programmable, reducing the OSR is equivalent to reducing the number of averaged samples in the subsequent decimation stage, and further teaches the required reduction).
Khoury and Rud teach an ADC method using a decimation filter to average digital samples, with the decimation period being an adjustable parameter. Ruha teaches that it is known to operate a sigma-delta modulator with a dynamically programmable oversampling ratio (OSR). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the adaptive OSR control logic taught by Ruha into the ADC method of Khoury and Rud, according to known methods. The motivation to do so is to implement a power-aware system: when signal strength is strong, as indicated by the system’s operational mode, the OSR (number of averaged samples) is predictably reduced to minimize power consumption and processing, while maintaining stability as taught by Ruha’s modulator, yielding expected predictable results (KSR).
Regarding dependent claim 17, Khoury, teaches:
The method of claim 15 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, is silent in regard to:
increasing the number of averaged samples based on a decrease in the signal strength of the analog sensor signal or the digital sensor signal.
However, Rud, in combination with Ruha, further teach:
increasing the number of averaged samples based on a decrease in the signal strength of the analog sensor signal or the digital sensor signal (Rud: [0015], [0021]-[0022], & [0024]-[0028]; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: teaches that the OSR (number of averaged samples) is a dynamically programmable parameter).
Khoury and Rud teach an ADC method with an adjustable decimation period (averaging length), Ruha provides the teaching that this averaging parameter (OSR) is dynamically programmable. It is well-established in the art of adaptive signal conversion that the number of averaged samples (OSR) should be increased when signal strength decreases, to maintain the necessary signal-to-noise ratio, and decreased when signal strength increases, to minimize power consumption. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the controller of Ruha to perform this specific adaptive adjustment within the ADC method of Khoury and Rud, according to known methods. This represents the standard optimization of an adaptive sigma-delta modulator to trade off power for performance based on real-time signal conditions, yielding expected predictable results (KSR).
Regarding dependent claim 18, Khoury, teaches:
The method of claim 15 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, is silent in regard to:
comparing the signal strength of the analog sensor signal or the digital sensor signal and one or more predefined threshold values, wherein the number of averaged samples is selected based on comparing the signal strength of the analog sensor signal or the digital sensor signal and the one or more predefined threshold values.
However, Rud, further teaches:
comparing the signal strength of the analog sensor signal or the digital sensor signal and one or more predefined threshold values (Fig. 2; [0010], [0014]-[0015], [0018]-[0019], & [Claim 1]: teaches comparing the monitored signal amplitude (signal strength) against specific noise amplitude thresholds (predefined threshold values)),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ADC circuit of Khoury by implementing the dynamic decimation filtering methodology taught by Rud, according to known methods. This modification represents the application of a known technique (dynamic decimation adjustment) to a known device, Khoury’s sensor ADC, to yield a predictable result: improved signal-to-noise (SNR) in the presence of time-varying environmental interference. The combination allows Khoury’s system to adaptively balance its digital filtering intensity against power consumption and signal bandwidth. When high-resolution filtering is required, the decimation period can be increased; when noise is low, the decimation period can be decreased. This trade-of is a well-known beneficial design strategy in the art of sigma-delta ADCs and technique for optimizing power consumption and noise performance in ADC signal processing chains, yielding expected predictable results (KSR) as taught by Rud.
However, Rud, in combination with Ruha, further teach:
wherein the number of averaged samples is selected based on comparing the signal strength of the analog sensor signal or the digital sensor signal and the one or more predefined threshold values ((Rud: [0010], [0014]-[0015], [0018]-[0019], [0024]-[0028], & [Claim 1]: teaches that the decimation period (number of averaged samples) is adjusted as a function of the detected signal characteristics; Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: teaches that the system is dynamically programmed to select converter parameters based on detected operational conditions).
Rud teaches the step of comparing a monitored signal amplitude (signal strength) against a predefined noise amplitude threshold. Rud, further teaches that the system adjusts the decimation period (number of averaged samples) based on detected signal dynamics. Ruha confirms that it is well-known to dynamically program ADC parameters, including the oversampling ratio (number of samples), based on the system’s operational mode, which is determined by evaluating signal conditions. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to implement the decimation adjustment of the Khoury/Rud/Ruha ADC by performing a comparison of the signal strength against predefined thresholds, as taught by Rud. Then using the result to dynamically select the number of averaged samples, as taught by Ruha, and yield expected predictable results (KSR). Based on the outcome of this comparison, the system dynamically selects and adjusts the decimation period (the number of averaged samples) within the sigma-delta decimation filter.
Regarding dependent claim 19, Khoury, teaches:
The method of claim 13 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, is silent in regard to:
determining a signal dynamic of the analog sensor signal or the digital sensor signal; and adjusting the number of averaged samples used to obtain the averaged sensor signal based on the signal dynamic.
However, Rud, further teaches:
determining a signal dynamic of the analog sensor signal or the digital sensor signal (Fig. 3; [0014]-[0015], [0018]-[0019], [0021]-[0022], [0024], & [0027]-[0028]);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ADC circuit of Khoury by implementing the dynamic decimation filtering methodology taught by Rud, according to known methods. This modification represents the application of a known technique, dynamic decimation adjustment, to a known device, Khoury’s sensor ADC, to yield a predictable result (KSR): improved signal-to-noise ratio (SNR) in the presence of time-varying environmental interference.
However, Rud, in combination with Ruha, further teach:
and adjusting the number of averaged samples used to obtain the averaged sensor signal based on the signal dynamic (Rud: [0024]-[0028]: teaches adjusting the decimation period (the number of averaged samples) in response to the detected frequency/dynamic (period P); Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: teaches that the adjustment is performed dynamically by a programmable controller in response to system/signal requirements).
Rud teaches the step of determining a signal dynamic, specifically the frequency period P of the sensor signal, and then adjusting the decimation period (the number of averaged samples) of the sigma-delta decimation filter based on the dynamic signal. Ruha confirms that it is well-known to implement such dynamic adjustments in a sigma-delta ADC using a programmable controller to vary parameters such as the oversampling ratio (number of samples) as a function of the detected operational mode or signal state. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the ADC method of Khoury and Rud to determine the signal dynamic as taught by Rud and perform the corresponding dynamic adjustment of the averaged samples as enabled by the teachings of Ruha. In order to optimize the system’s noise rejection relative to the temporal dynamics of the input signal, and yield expected predictable results (KSR).
Regarding dependent claim 20, Khoury, teaches:
The method of claim 19 (Fig. 1; [Abstract] & [0026]), further comprising:
Khoury, is silent in regard to:
performing a comparison of the signal dynamic of the analog sensor signal or the digital sensor signal and one or more predefined threshold values, wherein the number of averaged samples is selected based on the comparison.
However, Rud, further teaches:
performing a comparison of the signal dynamic of the analog sensor signal or the digital sensor signal and one or more predefined threshold values ([0003]-[0004], [0010], [0014]-[0015], [0018]-[0019], [0021]-[0022], [0024], [0027]-[0028], [Claim 1], [Claim 4], & [Claim 7]: teaches evaluating the signal dynamic (frequency period P) and comparing it against predefined operating thresholds to determine when an adjustment is necessary),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the ADC circuit of Khoury by implementing the dynamic decimation filtering methodology taught by Rud, according to known methods. This modification represents the application of a known technique (dynamic decimation adjustment) to a known device (Khoury’s sensor ADC) to yield a predictable result: improved signal-to-noise ratio (SNR) in the presence of time-varying environmental interference. The combination predictably allows Khoury’s system to adaptively balance its digital filtering intensity against power consumption and signal bandwidth. When high-resolution filtering is required, the decimation period can be increased; when noise is low, the decimation period can be decreased. In digital signal processing, mapping a measured continuous variable (e.g., frequency) to select a discrete hardware setting (e.g., a decimation rate) involves comparing the measured value to a lookup table of predefined thresholds or ranges. This combination represents the standard hardware architecture for an adaptive-bandwidth sigma-delta ADC, to achieve the predictable result of optimizing the decimation filter for the specific noise environment detected, yielding expected predictable results (KSR).
However, Rud, in combination with Ruha, further teach:
wherein the number of averaged samples is selected based on the comparison (Rud: [0024]-[0028]: teaches that the decimation period (the number of averaged samples) is a function of the detected signal dynamic); Ruha: [Abstract], [0005], [0007], [0024], [Claim 9], [Claim 21], & [Claim 32]: teaches that a programmable core selects this parameter (OSR/averaging) dynamically based on the system state).
Rud teaches the step of performing a comparison of a signal dynamic (the frequency period P) against predefined thresholds and using this comparison to trigger an adjustment of the decimation period (the number of averaged samples). Ruha teaches that such parameters such as the oversampling ratio or OSR are dynamically selected/programmed based on the comparison of the detected signal state. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to configure the ADC method of Khoury and Rud to perform this specific comparison and selection process. As it is the standard predictable method for implementing an adaptive-bandwidth sigma-delta ADC as disclosed by Ruha, and yield expected predictable results (KSR).
Conclusion
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/HUGO NAVARRO/Examiner, Art Unit 2858 May 21, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 5/29/2026
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