Prosecution Insights
Last updated: October 25, 2026
Application No. 18/894,346

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Sep 24, 2024
Priority
Mar 30, 2022 — JP 2022-057458 +1 more
Examiner
PAGE, STEVEN MITCHELL CHR
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Japan Display Inc.
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
390 granted / 466 resolved
+15.7% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
490
Total Applications
across all art units

Statute-Specific Performance

§101
3.9%
-36.1% vs TC avg
§103
39.4%
-0.6% vs TC avg
§102
34.7%
-5.3% vs TC avg
§112
21.0%
-19.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 466 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SEMICONDUCTOR DEVICE WITH INSULATING LAYER HAVING HIGH ALUMINUM CONCENTRATION. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki et al. (US 20130153892 A1, hereinafter Sasaki) With regards to claim 1, Sasaki discloses a semiconductor device (FIG. 3) comprising: a metal oxide layer (portion of metal oxide layer 402a directly over gate electrode 401) over an insulating surface; (portion of layer 402a directly contacting the substrate 400) an oxide semiconductor layer (SiNO film 402b) over the metal oxide layer; (See FIG. 3) and an insulating layer (oxide semiconductor layer 403) over the oxide semiconductor, wherein the insulating layer comprises a first region overlapping the oxide semiconductor layer, (See FIG. 3, showing the area where the layer 403 directly contacts the layer 402b) and a first aluminum concentration of the first region is greater than or equal to 1×1017 atoms/cm3. (Paragraph [0067]: “The concentration of aluminum in the oxide semiconductor film is lower than or equal to 1x10^18 atoms/cm^3.” Where the ranges overlap and would be obvious in view of the prior art) With regards to claim 2, Sasaki teaches the semiconductor device according to claim 1, wherein the first region is a region less than or equal to 50 nm from a surface of the insulating layer located on an opposite side of the oxide semiconductor layer. (See FIG. 3, where the region entirely overlaps the surface of the insulating layer 403) With regards to claim 7, Sasaki teaches the semiconductor device according to claim 1, wherein the metal oxide layer contains aluminum oxide. (Paragraph [0182]: “an aluminum oxide film as the gate insulating film 402a…”) Allowable Subject Matter Claims 3-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Sep 24, 2024
Application Filed
Sep 28, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12772619
DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
3y 1m to grant Granted Oct 20, 2026
Patent 12772596
SEMICONDUCTOR DEVICE HAVING STACKED STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
3y 1m to grant Granted Oct 20, 2026
Patent 12772441
MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
2y 3m to grant Granted Oct 20, 2026
Patent 12764929
MEMORY DEVICE AND METHOD OF FORMING THE SAME
3y 10m to grant Granted Oct 13, 2026
Patent 12765070
INTEGRATED CIRCUIT INCLUDING STANDARD CELLS AND METHOD OF DESIGNING THE SAME
3y 0m to grant Granted Oct 13, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
92%
With Interview (+8.8%)
2y 3m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 466 resolved cases by this examiner. Grant probability derived from career allowance rate.

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