DETAILED ACTION
This non-final office action is responsive to communications: application filed on 09/24/2024.
Claims 1-9 are pending. Claim 1 is independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the Applicant fully consider the references in entirety. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Applicant is requested to check other claim informality, language issues (e.g. antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
8. Claims 1-2, 4-5, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over McCrate et al. (US 2022/0130447 A1), in view of Fujioka et al. (US 2006/0291307 A1) and Hirose et al. (US 2018/0068735 A1).
Regarding independent claim 1, McCrate teaches a memory circuit (Fig. 1: 100 memory device with architecture shown in Fig. 2A, Fig. 3A, Fig. 3B) comprising:
a plurality of first bit lines (Fig. 2A: 204 first column/ bit line. Para [0030]) configured to be all connected together (Fig. 2A: operably connected via column decoder);
a plurality of second bit lines (Fig. 2A: 208 second column/ bit line. Para [0030]) configured to be all connect together (Fig. 2A: operably connected via column decoder);
a plurality of complementary cells (Fig. 2A: 121 “cell pair”. Para [0030], para [0013]) having
a first memory cell (Fig. 2A: 124 “first memory cell”) connected to a first bit line (Fig. 2A: 204) and a second memory cell (Fig. 2A: 127 “second memory cell”) connected to a second bit line (Fig. 2A: 208);
a first switch (Fig. 3A: column decoder switch) provided for each pair of first and second bit lines and connected to the first and second memory cells (see Fig. 2A and Fig. 3A: cell pair and associated bit lines are connected to SA via column decoder switch);
a first all bit line selection circuit operable, if an input test signal indicates a test, to turn on all the first switches regardless of bit data of an input switch control signal (McCrate teaches read, write operations using input switch control signal) and
a sensing circuit (Fig. 3A: 317 SA. Para [0036]) configured to be operable to sense a magnitude relationship (para [0036]: compare current) between a sum of currents flowing through the first bit lines (para [0036]: “…current…along the current path 308…”. See also Fig. 3A: current path 308 when first memory cell is selected by column decoder demarcation voltage) and a reference current (para [0036]: “reference current”. See also Fig. 3A: reference signal 321) and a magnitude relationship between a sum of currents flowing through the second bit lines (para [0036]: “…current…along the current path 308…”. See also Fig. 3A: current path 308 when second memory cell is selected by column decoder demarcation voltage) and the reference current (para [0036]: “reference current”. See also Fig. 3A: reference signal 321. See para [0034]-para [0036]: each cell can be individually compared. Also see McCrate Fig. 4 apparatus which meets this limitation where combined sense amps perform this function; sense amps being connected to paired cells 124, 127, reference line 438, sense switches 415 as described in para [0042], para [0043]),
wherein a gate of a first memory transistor included in the first memory cell and a gate of a second memory transistor included in the second memory cell are operable to be fed with a direct-current voltage (McCrate teaches first and second memory cells).
McCrate is silent with respect to the details of –
test circuitry, i.e., “a first all bit line selection circuit operable, if an input test signal indicates a test, to turn on all the first switches regardless of bit data of an input switch control signal”
Memory cell structure and function, i.e., “a gate of a first memory transistor included in the first memory cell and a gate of a second memory transistor included in the second memory cell are operable to be fed with a direct-current voltage”
Fujioka teaches a first all bit line selection circuit (Fig. 1: 38, 14, 24 combined test circuitry) operable, if an input test signal indicates a test (para [0080]: if Fig. 1: TES1 is received indicating “test mode”), to turn on all the first switches regardless of bit data of an input switch control signal (Fig. 4: circuitry and para [0080]: “…operation control circuit 24 receives the first burn-in test signal TES1 from the test pattern decoder 14, operates all write amplifiers to switch on all column switches CSW, operates all sense amplifiers SA to switch on all bit line transfer switches BT…”. When test mode is enabled, normal operation and associated signals are not used).
Hirose teaches a gate of a first memory transistor (Fig. 3B: T1) included in the first memory cell (Fig. 3B: 901. Para [0039]) and a gate of a second memory transistor (Fig. 3B: T2) included in the second memory cell (Fig. 3B: 902. Para [0039]) are operable to be fed with a direct-current voltage (Fig. 3B, TABLE II, para [0041]: GWL1 applied with dc voltage)
McCrate, Fujioka, and Hirose are in the same field of endeavor of memory read/ write operation & biasing and they are in analogous field of art. An ordinary skill in the art would understand the use of Fujioka and Hirose’s circuitry components into the apparatus of McCrate.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Fujioka’s test circuitry and Hirose’s memory cell structure into the apparatus of McCrate such that claimed limitations can be implemented. Motivation would be reliability test implementation in apparatus to “…reliably remove an inferior product…” (Fujioka para [0010]), and bitline disturb reduction by providing improved memory structure (Hirose para [0004], para [0005]).
Regarding claim 2, McCrate, Fujioka, and Hirose teach the memory circuit according to claim 1. McCrate, Hirose are silent with respect to remaining provisions of this claim.
Fujioka teaches wherein the sensing circuit includes a plurality of sensing circuits (Fig. 4: SA’s per column), the first bit lines (Fig. 4: BL’s), the second bit lines (Fig. 4: /BL’s), the complementary cells (Fig. 4: bit line and complementary bit line and associated cells), the first switches (Fig. 4: BT’s), and the first all bit line selection circuit (Fig. 1: 38, 14, 24 combined test circuitry signal routing to each column) are provided one each for each of the sensing circuits (Fig. 4: SA’s).
An ordinary skill in the art would understand that Fujioka’s component arrangement can be employed in the apparatus of McCrate, Fujioka, and Hirose.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate Fujioka’s teachings into the teachings of McCrate, Fujioka, and Hirose such that claimed limitation can be implemented in order to improve column control and test scheme.
Regarding claim 4, McCrate, Fujioka, and Hirose teach the memory circuit according to claim 1. Hirose teaches wherein the direct-current voltage is a first supply voltage (See Fig. 4, Fig. 5, TABLE II: WL hi voltage used on memory transistors is a dc voltage of high magnitude, generated from power supply VDD via voltage generator; and WL voltage is considered internal supply).
Regarding claim 5, McCrate, Fujioka, and Hirose teach the memory circuit according to claim 4. Hirose teaches wherein the first supply voltage is equal to a second supply voltage (Taken as any internal supply to internal circuitry e.g., WL driver which approximates WL voltage) necessary for the memory circuit to operate for a purpose other than to feed the direct-current voltage to the gate (Fig. 4, Fig. 5 supply shown used in internal circuitry).
Regarding claim 7, McCrate and Fujioka teach the memory circuit according to claim 1. Fujioka teaches wherein the direct-current voltage is a ground potential (See Fig. 4, Fig. 5: WL low voltage used on memory transistors is a dc voltage of zero).
Regarding claim 8, McCrate and Fujioka claim 1 apparatus. McCrate teaches an IC chip comprising: the memory circuit according to claim 1 (McCrate para [0015]: “semiconductor chip”).
9. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over McCrate et al. (US 2022/0130447 A1), Fujioka et al. (US 2006/0291307 A1) and Hirose et al. (US 2018/0068735 A1), in further view of Kawai et al. (US 2002/0044008A1)
Regarding claim 9, McCrate, Fujioka, Hirose teaches the memory circuit according to claim 1. They are silent with respect to remaining provisions of this claims. Kawai teaches apparatus comprising:
a second switch (Fig. 2: Sin for controlling reference current);
a reference current source (Fig. 2: 21); and
a diode-connected MOS transistor (Fig. 2: Q3) connected to the reference current source via the second switch (See Fig. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine Kawai’s teachings into the teachings of McCrate, Fujioka, and Hirose such that claimed limitation can be implemented in order to improve precision of reference signal used for sensing.
Allowable Subject Matter
Claims 3, and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations described in details in the following:
3. The memory circuit according to claim 1, wherein the first memory cell has a first selection transistor; the second memory cell has a second selection transistor; and the memory circuit includes a second all bit line selection circuit operable, if the input test signal indicates a test, to turn on all the pairs of first and second selection transistors regardless of bit data of an input read gate signal.
6. The memory circuit according to claim 5, further comprising: a first terminal to be fed with the first supply voltage; and a second terminal to be fed with the second supply voltage; wherein the first and second terminals are separate terminals.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
HAMA (US 2024/0331773 A1): Fig. 1-Fig. 11 disclosure is applicable for all claims. Hama a memory circuit that is provided to an IC chip, the memory circuit including: a complementary cell which includes a first memory cell that includes a first memory transistor, and a second memory cell that includes a second memory transistor; a reference cell which includes a reference transistor; a first terminal which is connectable to a gate of the first memory transistor and a gate of the second memory transistor, and to which a first power-supply voltage can be applied; a second terminal which is connectable to a gate of the reference transistor, and to which a second power-supply voltage can be applied; and a detection unit which detects a magnitude relationship between current that flows through the first memory cell or the second memory cell, and current that flows through the reference cell.
Kim et al. (US 2021/0142847 A1): Fig. 1-Fig. 6 disclosure is applicable for all claims. Kim teaches an electronic device (Fig. 7: 100 employing Fig. 1 SE structure. See Fig. 1-Fig. 8 for components and functionality) comprising: a plurality of memory cells (Fig. 7 SE’s) arranged in a plurality of memory cell pairs (Fig. 1: BC1), wherein a memory cell pair (Fig. 1: BC1 “bit cell”) is configured to store a single bit (bit cell stores one bit. See Fig. 6: Output) and wherein a first memory cell (Fig. 1: VRM11) in the memory cell pair stores a value (e.g. Fig. 6: LR) and a second memory cell (Fig. 1: VRM12) in the memory cell pair stores an inverse of the value (e.g. Fig. 6: HR).
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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