DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7, 9, and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard to claim 7, the claim recites “a portion drawn out from” in line 2 of the claim. It is unclear how a portion can be “drawn out”, rendering the claim indefinite. For the purposes of examination with regard to the prior art, this limitation will be treated as if referring to --a portion extending out from over--.
With regard to claim 9, the claim recites “a swelling portion swelling” at line 2 of the claim and “swelling portion” at lines 5-6 of the claim. It is unclear in what way there is any “swelling” in the claimed structure, rendering the claim indefinite. For the purposes of examination with regard to the prior art, the claimed swelling portion will be treated as if reciting a portion proximate to the barrier forming region.
With regard to claim 10, the claim depends from claim 9 and inherits its deficiencies. Furthermore, claim 10 also references a “swelling portion” at line 4 of the claim, which is indefinite for the same reasons as set forth above with regard to claim 9, and will be treated similarly.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5-13, and 15-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Pang et al. (US 2019/0103498).
With regard to claim 1, Pang teaches, in Fig 6, a semiconductor device comprising: a chip (10) having a principal surface (top surface in the figure); a pn-junction portion (boundary between 10 and 50) extending in a horizontal direction along the principal surface inside the chip; a trench insulating structure (210) formed in the principal surface such that the trench insulating structure penetrates through the pn-junction portion, and demarcating a diode region (region between elements 210) in the chip; a barrier forming region (region of 50 proximate to 175) formed in a surface layer portion of the principal surface in the diode region; and a metal layer (175) located on the principal surface such that the metal layer covers the barrier forming region in the diode region, and forming a Schottky-junction portion with the barrier forming region ([0071]).
With regard to claim 2, Pang teaches, in Fig 6, that the Schottky-junction portion is connected in reverse bias to the pn-junction portion ([0071]).
With regard to claim 5, Pang teaches, in Fig 6, a cathode region (135) formed in the surface layer portion of the principal surface and spaced from the barrier forming region in the diode region.
With regard to claim 6, Pang teaches, in Fig 6, a shallow trench insulating structure (150) formed between the barrier forming region and the cathode region in the principal surface.
With regard to claim 7, Pang teaches, in Fig 6, that the metal layer has a portion drawn out from the barrier forming region onto the shallow trench insulating structure (175 contacts 150, see figure).
With regard to claim 8, Pang teaches, in Fig 6, a guard region (110, 115) formed along the shallow trench insulating structure inside the chip, and having a conductivity type different from that of the cathode region ([0071]).
With regard to claim 9, Pang teaches, in Fig 6, that the guard region has a swelling portion swelling to the barrier forming region side from a portion along the shallow trench insulating structure, and the metal layer is electrically connected to the swelling portion of the guard region in the barrier forming region (at 115, see figures, [0050]).
With regard to claim 10, Pang teaches, in Fig 6, a high-concentration guard region (115) formed in a surface layer portion of the swelling portion, and having a higher impurity concentration than the guard region, wherein the metal layer is electrically connected to the high-concentration guard region in the barrier forming region ([0050]).
With regard to claim 11, Pang teaches, in Fig 6, that the shallow trench insulating structure surrounds the barrier forming region in a plan view, and the guard region surrounds the barrier forming region in a plan view (not shown, but discussed at [0012], [0039], [0059]).
With regard to claim 12, Pang teaches, in Fig 6, a sinker region (130) formed in the surface layer portion of the principal surface along the trench insulating structure in the diode region, and having the same conductivity type as that of the cathode region ([0052]).
With regard to claim 13, Pang teaches, in Fig 6, that the sinker region is connected to the cathode region ([0052]).
With regard to claim 15, Pang teaches, in Fig 6, a silicide layer formed in a portion covered by the metal layer in the barrier forming region (here taking an upper portion of 175 as the metal layer and a lower portion of 175 as the silicide layer).
With regard to claim 16, Pang teaches, in Fig 6, that the metal layer includes at least one of a Ti layer, a Ni layer, a Co layer, a Mo layer, and a W layer, and the silicide layer includes at least one of a TiSi layer, a TiSi2 layer, a NiSi layer, a CoSi layer, a CoSi2 layer, a MoSi2 layer, and a WSi2 layer ([0053]).
With regard to claim 17, Pang teaches, in Fig 6, that the metal layer is formed by a Co layer, and the silicide layer is formed by a CoSi2 layer ([0053]).
With regard to claim 18, Pang teaches, in Fig 6, a plurality of device regions (regions on the periphery of the figure, outside of elements 210) provided in the principal surface, wherein the trench insulating structure electrically isolates the diode region from the plurality of device regions (discussed at [0002], [0003], [0039]).
With regard to claim 19, Pang teaches, in Fig 6, that the plurality of device regions respectively include functional devices each forming a portion of an integrated circuit (discussed at [0002], [0003], [0039]).
With regard to claim 20, Pang teaches, in Fig 6, that the Schottky-junction portion forms a portion of the integrated circuit (discussed at [0002], [0003], [0039]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang et al. (US 2019/0103498) in view of Otsubo et al. (US 2020/0403072).
With regard to claim 3, Pang teaches most of the limitations of the claim, as set forth above with regard to claim 1.
Pang also teaches, in Fig 6, that the trench insulating structure includes a trench formed in the principal surface (210).
Pang does not explicitly teach an insulation film covering a side wall of the trench such that the insulation film exposes a portion of the chip from a bottom wall of the trench, and an embedded electrode embedded in the trench with the insulation film in between such that the embedded electrode is electrically connected to the chip at the bottom wall of the trench.
Otsubo teaches, in Figs 2 and 3, an insulation film (58) covering a side wall of the trench (8) such that the insulation film exposes a portion of the chip from a bottom wall of the trench (58a, [0056]), and an embedded electrode (59) embedded in the trench with the insulation film in between such that the embedded electrode is electrically connected to the chip at the bottom wall of the trench ([0057]) to, “reliably suppress or prevent leakage current between the first and second device regions. This configuration can, therefore, improve the region isolation performance, thereby improving the device properties of the respective first and second device regions,” ([0009]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Pang with the trench insulating structure configuration of Otsubo to improve region isolation performance and thus improve device properties.
With regard to claim 4, Otsubo teaches, in Figs 2 and 3, that the embedded electrode is made of conductive polysilicon ([0057]).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pang et al. (US 2019/0103498) in view of Nagoya et al. (WO 2009/153909, all citations made hereinafter are made to the attached machine translation).
With regard to claim 14, Pang teaches most of the limitations of the claim, as set forth above with regard to claim 12.
Pang does not explicitly teach that the sinker region is across the pn-junction portion in a thickness direction of the chip.
Nagoya teaches, in Fig 3 that the sinker region (13) is across the pn-junction portion (11a/11) in a thickness direction of the chip (page 10, paragraphs 1-3), “for taking out current by reducing the series resistance from the lower part to the upper part of the device, A lateral transistor that can be easily integrated can be formed on the same chip,” (page 5, paragraph 4).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Pang with the sinker disposition of Nagoya to ease further integration on the same chip.
Conclusion
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893
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