DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12 February 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5, 7, 9-11, 13, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto (US 2022/0330401), in view of Ogawa et al (US 2011/0068829; hereinafter Ogawa).
• Regarding claims 1 and 13, Hashimoto discloses a pixel circuit (figure 3) comprising:
a pulse width modulation circuit which generates a pulse width modulation signal (element 320 in figure 3 and ¶s 35 and 37),
wherein the pulse width modulation circuit includes an inverter (element 324 in figure 3 and ¶ 37) including:
a first sub-transistor (element 3241 in figure 3 and ¶ 38) including
a gate terminal connected to a first node (N1 in figure 3),
a first terminal which receives a driving voltage (VDD in figure 3), and
a second terminal connected to a second node (note the node formed between elements 325, 331, 333, 3241, and 3242 in figure 3); and
a second sub-transistor (element 3242 in figure 3 and ¶ 38) including
a gate terminal connected to the first node (N1 in figure 3),
a first terminal connected a third node (VSS in figure 3), and
a second terminal connected to the second node (note the node formed between elements 325, 331, 333, 3241, and 3242 in figure 3); and
a driving current generating circuit which generates a driving current whose a generation time is determined based on the pulse width modulation signal (elements 310, 330, and 340 in figure 3 and ¶s 36-39),
wherein the driving current generating circuit includes a light emitting element which emits a light based on the driving current (element 340 in figure 3),
wherein the first sub-transistor is a P-type transistor (element 3241 in figure 3) and further includes a gate terminal that is connected to the first node (note the relationship between N1 and element 3241 in figure 3), and
wherein the second sub-transistor is an N-type transistor (element 3242 in figure 3) and further includes a gate terminal that is connected to the first node (note the relationship between N1 and element 3242 in figure 3).
wherein an input terminal of the inverter is connected to the first node and an output terminal of the inverter is connected to the second node (figure 3),
wherein the inverter inverts a voltage of the first node and outputs an inverted voltage of the first node to the second node (¶ 38),
However, Hashimoto fails to disclose the additional details of the pixel.
In the same field of endeavor, Ogawa discloses where:
the first sub-transistor includes a back gate terminal which receives a first back gate voltage (element 22 in figure 12 and ¶s 92-95),
the second sub-transistor includes a back gate terminal which receives a second back gate voltage (element 21 in figure 12 and ¶s 92-95),
a threshold voltage of the first sub-transistor is determined based on the first back gate voltage and a threshold voltage of the second sub-transistor is determined based on the second back gate voltage (¶ 95), and
a difference between the threshold voltage of the first sub-transistor and the threshold voltage of the second sub-transistor is determined based on the voltage of the first node which is the first back gate voltage and the second back gate voltage (inherent in ¶ 95; where, even though Ogawa does not mention a “difference” between threshold voltages, the difference between threshold voltages is determined based on the first input voltage because each individual threshold voltage is based on the first input voltage).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Hashimoto according to the teachings of Ogawa, for the purpose of controlling the threshold voltage of an inverter based on the input of the inverter so as to facilitate a high-speed switching operation of the inverter (¶ 95).
• Regarding claims 2, 3, 5, 7, 9-11, 14, and 19, Hashimoto, in view of Ogawa, discloses everything claimed, as applied to claims 1 and 13. Additionally, Hashimoto discloses where:
Claim 3: the pixel circuit further comprises:
a second transistor (element 325 in figure 3 and ¶ 37) including
a gate terminal which receives a second gate signal (SPWM in figure 3),
a first terminal which receives a data voltage including a pulse width modulation data voltage and a sweep voltage (¶ 37), and
a second terminal connected to a third node (note the node formed between elements 325, 331, 333, 3241, and 3242 in figure 3); and
a boost capacitor including a first terminal connected to the third node and a second terminal connected to the first node (element 323 in figure 3 and ¶ 37).
Claim 5: a driving current is generated based on the data voltage and a generation time of the driving current is determined depending on a voltage level of the pulse width modulation data voltage (¶s 36-39).
However, Hashimoto fails to disclose the additional details of the pixel.
In the same field of endeavor, Ogawa discloses where:
Claims 2 & 14: each of the first back gate voltage and the second back gate voltage is equal to a voltage of the first node (figure 12 and ¶ 92).
Claims 7 & 19: the inverter reduces a delay time of a rising period of the driving current and a delay time of a falling period of the driving current (at least suggested by “high speed” in ¶ 95, in view of at least ¶s 6 and 7).
Claim 9: the threshold voltage of the first sub-transistor increases when the first back gate voltage decreases (¶ 67).
Claim 10: the threshold voltage of the second sub-transistor decreases when the second back gate voltage increases (¶ 67).
Claim 11: a delay time of a rising period of the driving current and a delay time of a falling period of the driving current decrease when a difference between the threshold voltage of the first sub-transistor and the threshold voltage of the second sub-transistor decreases (at least suggested by “high speed” in ¶ 95, in view of at least ¶s 6, 7, and 67).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Hashimoto according to the teachings of Ogawa, for the purpose of controlling the threshold voltage of an inverter based on the input of the inverter so as to facilitate a high-speed switching operation of the inverter (¶ 95).
Claims 12 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Hashimoto, in view of Ogawa, and further in view of Shin et al (US 2018/0190204; hereinafter Shin).
• Regarding claims 12 and 22, Hashimoto, in view of Ogawa, discloses everything claimed, as applied to claims 1 and 13, respectively. However, Hashimoto, in view of Ogawa, fails to disclose the additional details of the pixel.
In the same field of endeavor, Shin discloses where:
Claims 12 & 22: the P-type transistor is a polysilicon thin-film transistor (¶s 128-133) and
the N-type transistor is an oxide thin-film transistor (¶s 128-133).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have modified the invention of Hashimoto, as modified by Ogawa, according to the teachings of Shin, for the purposes of decreasing power consumption and improving the reliability of an inverter circuit (¶s 129 and 133).
Allowable Subject Matter
Claims 15 and 16 are allowed for the reasons found in the Office action mailed 17 June 2025.
Response to Arguments
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the back-gate voltages independently set the threshold voltages of the P-type and N-type devices, and that the inverter input is at the first node while the back-gate terminals are separately addressed” and “gate tied to the inverter input node with independently biased, non-tied back gates for both devices” (bottom of page 9 filed 20 January 2026)) are not recited in the rejected claims. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Closing Remarks/Comments
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN DANIELSEN whose telephone number is (571)272-4248. The examiner can normally be reached Monday-Friday 9:00 AM to 5:00 PM Eastern Time.
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/NATHAN DANIELSEN/Primary Examiner, Art Unit 2622