CTNF 18/895,148 CTNF 92465 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 5-7, 9, 11, 13 and 17 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by “Manusharow” (US 2014/0251669) . Regarding claim 1, Manusharow anticipates 1. A wiring board, comprising: a build-up layer comprising; a first insulation layer having a first surface and a second surface located opposite to the first surface (Fig. 3, [0017], [0020]; the substrate 162 is a build-up layer comprising; a first insulation layer having a first surface and a second surface located opposite to the first surface) ; and a first electrical conductor layer located on the first surface (Fig. 3, [0024]; the bond pads 172 is a first electrical conductor layer located on the first surface) ; and a solder resist covering a portion of, the first surface and the first electrical conductor layer (Fig. 3, [0020]; the portion of the substrate 162 that covers a portion of the first surface and the bond pads 172) , wherein the build-up layer comprises a mounting region on the first surface in which an electronic component comprising an inductor is to be mounted (Fig. 3, [0024]; the substrate 162 a mounting region on the first surface in which an electronic component 130 comprising an inductor 142 is to be mounted) , the mounting region comprises a first region at a location opposite to the inductor when the electronic component is mounted (Fig. 3, [0019]; the mounting region comprises the substrate opening 164 which is a first region at a location opposite to the inductor 142 when the electronic component 130 is mounted) , and the first electrical conductor layer and the solder resist are not located in the first region (Fig. 3, [0024]; the bond pads 172 and the portion of the substrate 162 are not located in the substrate opening 164) . Regarding claim 2, Manusharow anticipates 2. The wiring board according to claim 1, wherein the build-up layer comprises a recessed portion opening in the first region (Fig. 3, [0019]; the substrate 162 comprises a recessed portion opening, the substrate opening 164, in the first region) . Regarding claim 3, Manusharow anticipates 3. The wiring board according to claim 2, wherein a bottom portion of the recessed portion is located in the first insulation layer (Fig. 3, [0019]; a bottom portion of the substrate opening 164 is located in the substrate 162) . Regarding claim 5, Manusharow anticipates 5. The wiring board according to claim 1, wherein the solder resist comprises a wall projecting in a direction opposite to the first surface and surrounding the first region (Fig. 3, [0019]; the substrate 162 comprises a wall in the substrate opening 164 projecting in a direction opposite to the first surface and surrounding the first region) . Regarding claim 6, Manusharow anticipates 6. The wiring board according to claim 2, wherein the solder resist comprises a wall projecting in a direction opposite to the first surface and surrounding the first region (Fig. 3, [0019]; the substrate 162 comprises a wall in the substrate opening 164 projecting in a direction opposite to the first surface and surrounding the first region) . Regarding claim 7, Manusharow anticipates 7. The wiring board according to claim 3, wherein the solder resist comprises a wall projecting in a direction opposite to the first surface and surrounding the first region (Fig. 3, [0019]; the substrate 162 comprises a wall in the substrate opening 164 projecting in a direction opposite to the first surface and surrounding the first region) . Regarding claim 9, Manusharow anticipates 9. A mounting structure, comprising: a wiring board according to claim 1 (Fig. 3, [0019] the substrate 162 is a motherboard according to claim 1) ; and an electronic component located on the mounting region of the wiring board (Fig. 3, [0024]; the electronic component 130 is located on the mounting region of the substrate 162) , the electronic component comprising an inductor facing the first region through an air gap between the inductor and the wiring board (Fig. 3, [0024]; the electronic component 130 comprising an inductor 142 facing the first region through an air gap between the inductor 142 and the substrate 162) . Regarding claim 11, Manusharow anticipates 11. A mounting structure, comprising: a wiring board according to claim 2 (Fig. 3, [0019] the substrate 162 is a motherboard according to claim 2) ; and an electronic component located on the mounting region of the wiring board (Fig. 3, [0024]; the electronic component 130 is located on the mounting region of the substrate 162) , the electronic component comprising an inductor facing the first region through an air gap between the inductor and the wiring board (Fig. 3, [0024]; the electronic component 130 comprising an inductor 142 facing the first region through an air gap between the inductor 142 and the substrate 162) . Regarding claim 13, Manusharow anticipates 13. A mounting structure, comprising: a wiring board according to claim 3 (Fig. 3, [0019] the substrate 162 is a motherboard according to claim 3) ; and an electronic component located on the mounting region of the wiring board (Fig. 3, [0024]; the electronic component 130 is located on the mounting region of the substrate 162) , the electronic component comprising an inductor facing the first region through an air gap between the inductor and the wiring board (Fig. 3, [0024]; the electronic component 130 comprising an inductor 142 facing the first region through an air gap between the inductor 142 and the substrate 162) . Regarding claim 17, Manusharow anticipates 17. A mounting structure, comprising: a wiring board according to claim 5 (Fig. 3, [0019] the substrate 162 is a motherboard according to claim 5) ; and an electronic component located on the mounting region of the wiring board (Fig. 3, [0024]; the electronic component 130 is located on the mounting region of the substrate 162) , the electronic component comprising an inductor facing the first region through an air gap between the inductor and the wiring board (Fig. 3, [0024]; the electronic component 130 comprising an inductor 142 facing the first region through an air gap between the inductor 142 and the substrate 162) . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 4, 8, 10, 12, 14-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Manusharow in view of “Proschwitz” (US2023/0300975) . Regarding claim 4, Manusharow discloses the claimed invention as applied to claim 2, above. Manusharow does not disclose the limitations of claim 4. Proschwitz discloses 4. The wiring board according to claim 2, wherein the build-up layer further comprises a second insulation layer in contact with the second surface (Fig. 2, [0027]-[0028], [0037]; the bottom surface of the cavity 108E is in contact with the second surface) ; and a second electrical conductor layer located between the first insulation layer and the second insulation layer (Fig. 2, [0027]-[0028], [0037]; the pads at the bottom surface of the cavity 108D is between first and second insulation layers) , and the bottom portion of the recessed portion is in the second electrical conductor layer (Fig. 2, [0027]-[0028], [0037]; the bottom surface of the cavity 108E is in the second electrical conductor layer) . It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Manusharow’s wiring board with Proschwitz’s circuit package in order for the circuit board and the components to be minimized which may help achieve reliable attachment of multiple dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Further, various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches, as suggested by Proschwitz at [0019]. Regarding claim 8, Manusharow in view of Proschwitz discloses the claimed invention as applied to claim 4, above. Manusharow discloses 8. The wiring board according to claim 4, wherein the solder resist comprises a wall projecting in a direction opposite to the first surface and surrounding the first region (Fig. 3, [0019]; the substrate 162 comprises a wall in the substrate opening 164 projecting in a direction opposite to the first surface and surrounding the first region) . Regarding claim 10, Manusharow discloses the claimed invention as applied to claim 9, above. Manusharow does not disclose the limitations of claim 10. Proschwitz discloses 10. The mounting structure according to claim 9, wherein an underfill is located between the electronic component and the wiring board (Fig. 2, [0027]-[0028], [0037]; the underfill material 160 is located between the die 114-5 and the circuit board 133) . It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Manusharow’s wiring board with Proschwitz’s circuit package in order for the circuit board and the components to be minimized which may help achieve reliable attachment of multiple dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Further, various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches, as suggested by Proschwitz at [0019]. Regarding claim 12, Manusharow discloses the claimed invention as applied to claim 11, above. Manusharow does not disclose the limitations of claim 12. Proschwitz discloses 12. The mounting structure according to claim 11, wherein an underfill is located between the electronic component and the wiring board (Fig. 2, [0027]-[0028], [0037]; the underfill material 160 is located between the die 114-5 and the circuit board 133) . It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Manusharow’s wiring board with Proschwitz’s circuit package in order for the circuit board and the components to be minimized which may help achieve reliable attachment of multiple dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Further, various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches, as suggested by Proschwitz at [0019]. Regarding claim 14, Manusharow discloses the claimed invention as applied to claim 13, above. Manusharow does not disclose the limitations of claim 14. Proschwitz discloses 14. The mounting structure according to claim 13, wherein an underfill is located between the electronic component and the wiring board (Fig. 2, [0027]-[0028], [0037]; the underfill material 160 is located between the die 114-5 and the circuit board 133) . It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Manusharow’s wiring board with Proschwitz’s circuit package in order for the circuit board and the components to be minimized which may help achieve reliable attachment of multiple dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Further, various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches, as suggested by Proschwitz at [0019]. Regarding claim 15, Manusharow in view of Proschwitz discloses the claimed invention as applied to claim 4, above. Manusharow discloses 15. A mounting structure, comprising: a wiring board according to claim 4 (Fig. 3, [0019] the substrate 162 is a motherboard according to claim 4) ; and an electronic component located on the mounting region of the wiring board (Fig. 3, [0024]; the electronic component 130 is located on the mounting region of the substrate 162) , the electronic component comprising an inductor facing the first region through an air gap between the inductor and the wiring board (Fig. 3, [0024]; the electronic component 130 comprising an inductor 142 facing the first region through an air gap between the inductor 142 and the substrate 162) . Regarding claim 16, Manusharow in view of Proschwitz discloses the claimed invention as applied to claim 15, above. Manusharow does not disclose the limitations of claim 16. Proschwitz discloses 16. The mounting structure according to claim 15, wherein an underfill is located between the electronic component and the wiring board (Fig. 2, [0027]-[0028], [0037]; the underfill material 160 is located between the die 114-5 and the circuit board 133) . Regarding claim 18, Manusharow discloses the claimed invention as applied to claim 17, above. Manusharow does not disclose the limitations of claim 18. Proschwitz discloses 18. The mounting structure according to claim 17, wherein an underfill is located between the electronic component and the wiring board (Fig. 2, [0027]-[0028], [0037]; the underfill material 160 is located between the die 114-5 and the circuit board 133) . It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Manusharow’s wiring board with Proschwitz’s circuit package in order for the circuit board and the components to be minimized which may help achieve reliable attachment of multiple dies at a lower cost, with improved power efficiency, with higher bandwidth, and/or with greater design flexibility, relative to conventional approaches. Further, various ones of the microelectronic assemblies disclosed herein may exhibit better power delivery and signal speed while reducing the size of the package relative to conventional approaches, as suggested by Proschwitz at [0019]. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANLEY TSO whose telephone number is (571)270-0723. The examiner can normally be reached Tu-Thurs 6am-6pm, alt M 6am-2pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tim Thompson can be reached at 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANLEY TSO/Primary Examiner, Art Unit 2847 Application/Control Number: 18/895,148 Page 2 Art Unit: 2847 Application/Control Number: 18/895,148 Page 3 Art Unit: 2847 Application/Control Number: 18/895,148 Page 4 Art Unit: 2847 Application/Control Number: 18/895,148 Page 5 Art Unit: 2847 Application/Control Number: 18/895,148 Page 6 Art Unit: 2847 Application/Control Number: 18/895,148 Page 7 Art Unit: 2847 Application/Control Number: 18/895,148 Page 8 Art Unit: 2847 Application/Control Number: 18/895,148 Page 9 Art Unit: 2847 Application/Control Number: 18/895,148 Page 10 Art Unit: 2847 Application/Control Number: 18/895,148 Page 11 Art Unit: 2847
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