DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed June 4, 2026.
Claims 1-10 are pending. Claims 1 and 3-6 are amended. Claims 1 and 4 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on November 4, 2024.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nagey (U.S. 2016/0133321) in view of Yin et al. (U.S. 2025/0037763; hereinafter “Yin”).
Regarding independent claim 1, Nagey teaches a method for parallel analog in-memory computing (see page 1, par. 0016), comprising the following steps:
inputting an analog current signal (“Each data signal is represented as one of current values (currents, bit line currents, memory cell outputs) 263-266,” see page 4, par. 0046);
replicating the analog current signal by a replication module (Fig. 2: 271-274) to form a corresponding replicated current signal (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045), and performing weighted processing of all replicated current signals to obtain a corresponding set of modulated current signals (“Currents I0, I1, I2 and I3 are binarized while flowing through binarizer 270 generating binary weighted currents..283-286,” see page 4, par. 0046), wherein the replication module comprises a first transistor and a second transistor which form a current mirror circuit (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045); and
performing weighted accumulated operation of a set of modulated current signals according to Kirchhoff’s current law to obtain an output current signal (see page 4, par. 0046),
wherein performing the weighted processing of the replicated current signals comprises:
performing weight assignment through a switch element (Resistive memory elements are programmed in high and low resistance state respectively. In both cases a current flows through the resistive memory element. The current is inversely proportional to resistance, i.e. when the resistive memory element is in a low-resistance state, the current can be equal to the input current, and when the resistive memory element is in a high resistance state, the current will be lower, see also pages 2-3, par. 0040-0042).
However, Nagey is silent with respect to wherein an output end of the switch element is directly connected to an input end of the first transistor included in the replication module.
Similar to Nagey, Yin teaches a method for in-memory computing and tuning the conductance of each cross-point device to a specific value (also referred to as “weight”) (see page 2, par. 0023 and page 4, par. 0049).
Furthermore, Yin teaches performing weight assignment through a switch element (Fig. 4: 430), wherein an output end of the switch element is directly connected to an input end of the first transistor included in the replication module (Fig. 4: 420).
Since Yin and Nagey are from the same field of endeavor, the teachings described by Yin would have been recognized in the pertinent art of Nagey.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Yin with the teachings of Nagey for the purpose of improve the ADC’s performance, see Yin’s pages 4-5, par. 0055.
Regarding claim 2, Nagey in combination with Yin teaches the limitations with respect to claim 1.
Furthermore, Nagey teaches wherein the analog current signal is replicated through a current replication circuit to form the corresponding replicated current signal Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045).
Regarding claim 3, Nagey in combination with Yin teaches the limitations with respect to claim 2.
Nagey teaches wherein when the switching element is in a low-resistance state, an output modulated current signal equals an input current signal, representing that the input current signal is assigned with a weight or “1”; and
wherein when the switching element is in a high-resistance state, the output modulated current signal is far less than the input current signal, representing that the input current signal is assigned with a weight of “0” (Resistive memory elements are programmed in high and low resistance state respectively. In both cases a current flows through the resistive memory element. The current is inversely proportional to resistance, i.e. when the resistive memory element is in a low-resistance state, the current can be equal to the input current, and when the resistive memory element is in a high resistance state, the current will be lower, see also pages 2-3, par. 0040-0042).
Regarding independent claim 4, Nagey teaches a device (Fig. 2) for parallel analog in-memory computing, comprising:
single-bit units, wherein each of the single-bit units comprises a replication module (Fig. 2: 271-274) and a switch module (Fig. 2: 210, 225, 275-278), the replication module is configured for replicating an analog current signal to form a replicated current signal (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045), and the switch module is configured for performing weighted processing of replicated current signals to obtain a set of modulated current signals (“Currents I0, I1, I2 and I3 are binarized while flowing through binarizer 270 generating binary weighted currents..283-286,” see page 4, par. 0046), wherein the replication module comprises a first transistor and a second transistor which form a current mirror circuit (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045), wherein the weighted processing is performed by performing weight assignment through a switch element included in the switch module (Resistive memory elements are programmed in high and low resistance state respectively. In both cases a current flows through the resistive memory element. The current is inversely proportional to resistance, i.e. when the resistive memory element is in a low-resistance state, the current can be equal to the input current, and when the resistive memory element is in a high resistance state, the current will be lower, see also pages 2-3, par. 0040-0042) and
weighted modules, configured for performing weighted accumulated operation of the set of modulated current signals according to Kirchhoff’s current law to obtain an output current signal (Fig. 2: 270 and 280, see page 4, par. 0046).
However, Nagey is silent with respect to wherein an output end of the switch element is directly connected to an input end of the first transistor included in the replication module.
Similar to Nagey, Yin teaches a device for in-memory computing and tuning the conductance of each cross-point device to a specific value (also referred to as “weight”) (see page 2, par. 0023 and page 4, par. 0049).
Furthermore, Yin teaches performing weight assignment through a switch element (Fig. 4: 430), wherein an output end of the switch element is directly connected to an input end of the first transistor included in the replication module (Fig. 4: 420).
Since Yin and Nagey are from the same field of endeavor, the teachings described by Yin would have been recognized in the pertinent art of Nagey.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Yin with the teachings of Nagey for the purpose of improve the ADC’s performance, see Yin’s pages 4-5, par. 0055.
Regarding claim 5, Nagey in combination with Yin teaches the limitations with respect to claim 4.
Furthermore, Nagey teaches wherein the replication module is further configured for outputting the replicated current signal of a fixed size (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045).
Regarding claim 6, Nagey in combination with Yin teaches the limitations with respect to claim 5.
Furthermore, Nagey teaches wherein the current mirror circuit of the replication module replicates the input current at a ratio of 1:1 or any other fixed ratio (see page 5, par. 0050).
Regarding claim 7, Nagey in combination with Yin teaches the limitations with respect to claim 5.
Furthermore, Nagey teaches wherein the switch module comprises a memristor or a non-volatile memory, and the non-volatile memory is one or more of MRAM, PCM and FLASH (see page 3, par. 0044).
Regarding claim 8, Nagey in combination with Yin teaches the limitations with respect to claim 4.
Furthermore, Nagey teaches wherein each of the weighted modules performs weighted summation of output modulated current signals from n switch modules respectively with 2i as weighted values, where n is an integer and I is an integer ranging from 0 to n-1, to obtain an output current signal with an n-bit precision (see page 1, par. 0010).
Regarding claim 9, Nagey in combination with Yin teaches the limitations with respect to claim 8.
Furthermore, Nagey teaches wherein an electronic element of each of the weighted modules is one or more of the memristor, the MRAM, the PCM and the FLASH (see Abstract, “binarizer coupled to the memory array assigns binary weights,” see also page 3, par. 0044).
Regarding claim 10, Nagey in combination with Yin teaches the limitations with respect to claim 5.
Furthermore, Nagey teaches wherein replication modules and switch modules included in the single-bit units form a crossbar array (see Fig. 2).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825
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