DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed September 24, 2024.
Claims 1-10 are pending. Claims 1 and 4 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on November 4, 2024.
Claim Objections
Claim 4 is objected to because of the following informalities: claim 4 is construed as independent claim drafted in a short-hand format to avoid rewriting the elements recited in claim 1. For proper fee calculation, claim 4 should be canceled or redraft it as independent claim including all the limitations of claim 1. See Ex parte Porter, 25 U.S.P.Q.2d 1147 (Bd. of Pat. App. Inter. 1992).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nagey (U.S. 2016/0133321).
Regarding independent claim 1, Nagey discloses a method for parallel analog in-memory computing (see page 1, par. 0016), comprising the following steps:
inputting an analog current signal (“Each data signal is represented as one of current values (currents, bit line currents, memory cell outputs) 263-266,” see page 4, par. 0046);
replicating the analog current signal to form a corresponding replicated current signal (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045), and performing weighted processing of all replicated current signals to obtain a corresponding set of modulated current signals (“Currents I0, I1, I2 and I3 are binarized while flowing through binarizer 270 generating binary weighted currents..283-286,” see page 4, par. 0046); and
performing weighted accumulated operation of a set of modulated current signals according to Kirchhoff’s current law to obtain an output current signal (see page 4, par. 0046).
Regarding claim 2, Nagey discloses wherein the analog current signal is replicated through a current replication circuit to form the corresponding replicated current signal Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045).
Regarding claim 3, Nagey discloses wherein the weighted processing of all replicated current signals is detailed as follows:
performing weight assignment through a switch module, wherein the switch module comprises a switching element;
wherein when the switching element is in a low-resistance state, an output modulated current signal equals an input current signal, representing that the input current signal is assigned with a weight or “1”; and
wherein when the switching element is in a high-resistance state, the output modulated current signal is far less than the input current signal, representing that the input current signal is assigned with a weight of “0” (Resistive memory elements are programmed in high and low resistance state respectively. In both cases a current flows through the resistive memory element. The current is inversely proportional to resistance, i.e. when the resistive memory element is in a low-resistance state, the current can be equal to the input current, and when the resistive memory element is in a high resistance state, the current will be lower, see also pages 2-3, par. 0040-0042).
Regarding independent claim 4, Nagey discloses a device (Fig. 2) using the method for parallel analog in-memory computing according to claim 1, comprising:
single-bit units, configured for replicating and weighted processing of analog current signals to obtain a set of modulated current signals (Fig. 2: 201 and 270, see pages 3-4, par. 0045), and
weighted modules, configured for performing weighted accumulated operation of the set of modulated current signals according to Kirchhoff’s current law to obtain an output current signal (Fig. 2: 270 and 280, see page 4, par. 0046).
Regarding claim 5, Nagey discloses wherein each of the single-bit units comprises a replication module (Fig. 2: 271-274) and a switch module (Fig. 2: 210, 225, 275-278);
the replication module is configured for replicating the analog current signal and outputting the replicated current signal of a fixed size (Fig. 2: Binarizer 270 comprises load transistors 217 and 278 to form a current copier…commonly known in the art as a current mirror, see page 3-4, par. 0045); and
the switch module is configured for performing the weighted processing of the replicated current signal (“Currents I0, I1, I2 and I3 are binarized while flowing through binarizer 270 generating binary weighted currents..283-286,” see page 4, par. 0046).
Regarding claim 6, Nagey discloses wherein the replication module is a current mirror circuit that replicates the input current at a ratio of 1:1 or any other fixed ratio (see page 5, par. 0050).
Regarding claim 7, Nagey discloses wherein the switch module comprises a memristor or a non-volatile memory, and the non-volatile memory is one or more of MRAM, PCM and FLASH (see page 3, par. 0044).
Regarding claim 8, Nagey discloses wherein each of the weighted modules performs weighted summation of output modulated current signals from n switch modules respectively with 2i as weighted values, where n is an integer and I is an integer ranging from 0 to n-1, to obtain an output current signal with an n-bit precision (see page 1, par. 0010).
Regarding claim 9, Nagey discloses wherein an electronic element of each of the weighted modules is one or more of the memristor, the MRAM, the PCM and the FLASH (see Abstract, “binarizer coupled to the memory array assigns binary weights,” see also page 3, par. 0044).
Regarding claim 10, Nagey discloses wherein replication modules and switch modules included in the single-bit units form a crossbar array (see Fig. 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
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/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825