Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112(a)
1. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 21, 33 and 38 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claims include the following language – “wherein the third to seventh transistor are between the first wire and the second wire in a plan view”. However the specification does not include any “plan views” as discussed below.
The term “plan” does not exist in the applicant’s specification. The common dictionary definition of “plan view” is a noun: the appearance of an object as seen from above1.
Applicant’s specification - [0037] In the following detailed description, only certain example embodiments have been shown and described, simply by way of illustration. …. the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. Claim 21 and 33 are drawn to a scan driver” and claim 38 is drawn to a “display device which comprises a scan driver” yet none of the drawings described by the applicant are a “plan view” of a scan driver and /or display. None of the drawings describe an orientation and as noted above, even the applicant discounts the accuracy of the drawings. The Office requests a correction is made to either the claim language or the specification and drawings. The Office suggests using the words in “a layout view” to correct the deficiency.
Claims 22-32; 34-37 and 39-40 depend from claims 21, 33 and 38 and as such suffer from the same deficiencies.
Claim Rejections - 35 USC § 112(b)
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21, 33 and 38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims each claim that a “plan view” exists of an object. There are no drawings in the application which are “plan views”. The Office requests appropriate action is taken to clarify the drawings and or specification.
Claims 22-32; 34-37 and 39-40 depend from claims 21, 33 and 38 and as such suffer from the same deficiencies.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21 and 38 rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1 of U.S. Patent No. 10,943,538. Although the claims at issue are not identical, they are not patentably distinct from each other because as shown by the table below the present application subject matter as presently claimed is disclosed the cited patent.
Application #: 18/895,328 US Patent #: 10,943,538
A scan driver comprising:
A scan driver comprising:
a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits comprising:
a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits comprising:
a first transistor configured to receive an input signal in response to a first clock signal and output a second clock signal based on an enable level of the input signal;
a first transistor configured to receive an input signal in synchronization with a first clock signal and to respond to an enable level of the input signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal;
a second transistor electrically connected between the first transistor and a first voltage;
a second transistor electrically connected between the first transistor and a first voltage;
a third transistor electrically connected between a gate of the second transistor and a second voltage;
a third transistor electrically connected between a gate of the second transistor and a second voltage;
and a fourth transistor electrically connected between a gate of the first transistor and the first voltage;
a first capacitor and a second capacitor;
first wire configured to transfer the first clock signal;
a second wire configured to transfer the second clock signal;
a first wire configured to transfer the first voltage;
a third wire configured to transfer the first voltage;
and a second wire configured to transfer the second voltage,
and a fourth wire configured to transfer the second voltage,
wherein the first wire and the second wire are on a first side of the first transistor and the second transistor in a plan view.
See Fig. 1 (the Office also notes as discussed above there is no “plan view” of the applicant’s invention in the present application)
wherein a width of the third wire is larger than a width of the fourth wire, wherein the first voltage and the second voltage are DC voltages and the first voltage is higher than the second voltage, wherein the first, second, third, and fourth transistor are p-channel transistors.
Possible Allowable Subject Matter
4. Claims 33 -37 are allowable if the applicant traverses or otherwise overcomes the above rejection of base claims as cited above. After a search the Office was unable to find prior art which disclosed Claim 33. The representative closest prior art is Park US Patent Application (20120182283) found to date, which alone, or in combination, does not provide a teaching, a suggestion or a motivation that could be found either in the art or within the skill of one of ordinary skill in the art at the time of the invention to modify or combine the prior art to disclose the cited claim limitations above and more specifically ““a fourth transistor electrically connected between a gate of the first transistor and the first voltage. a fifth transistor electrically connected between the fourth transistor and the gate of the first transistor. a sixth transistor electrically connected between a gate of the second transistor and a gate of the third transistor. a seventh transistor for transferring the input signal to a gate of the first transistor in response to the first clock signal” of the claimed invention. Claims 34-37 depend from claim 33 and similarly would be allowed when the independent claims are in position for allowance, if the applicant traverses or otherwise overcomes the above rejection of base claim 33.
5. Claims 24-27 and 39 and 40 would be allowable if the applicant traverses or otherwise overcomes the above rejection of base claims 21 and 38. The applicant must properly traverse the double patenting rejection prior to any final disposition can be determined regarding the application, however the claims as presently presented are not disclose or suggested by any prior art or combination any prior art, to found to date.
As the claims are presently present the representative closest prior art is Park US Patent Application (20120182283), alone, or in combination, do not provide a teaching, a suggestion or a motivation that could be found either in the art or within the skill of one of ordinary skill in the art at the time of the invention to modify or combine the prior art to disclose the cited claim limitations above and more specifically “a fourth transistor electrically connected between a gate of the first transistor and the first voltage. a fifth transistor electrically connected between the fourth transistor and the gate of the first transistor. a sixth transistor electrically connected between a gate of the second transistor and a gate of the third transistor. a seventh transistor for transferring the input signal to a gate of the first transistor in response to the first clock signal” of the claimed invention. Claims 34-37 depend from claim 33 and similarly would be allowed when the independent claims are in position for allowance.
Claim Rejections - 35 USC § 102
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use,
invention.
8. Claim(s) 21-24 and 38 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al US Patent Application
Regarding claim 21 Park teaches a scan driver comprising: a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits the scan driver 200 of FIG. 1 includes a plurality of stages ST1-STn [Park para 0060 and see Fig. 2] comprising: a first transistor configured to receive an input signal in response to a first clock signal and output a second clock signal based on an enable level of the input signal The first transistor is connected between a first control terminal supplied with a voltage of a first level or a second level and an output terminal for outputting a scan signal having a voltage according to the voltage of the first control terminal, and the first transistor has a gate connected to a first node. [Park para 0024 and see Fig. 3]; a second transistor electrically connected between the first transistor and a first voltage The third transistor is connected to a first voltage terminal supplied with a first voltage and the output terminal, and the first transistor has a gate connected to a second node [Park para 0024 and see Fig. 3]; a third transistor electrically connected between a gate of the second transistor and a second voltage The second transistor is connected between a second control terminal supplied with the voltage of the first level or the second level and the first node, and the second transistor has a gate connected to the second control terminal. [Park para 0024 and see Fig. 3]; a first wire configured to transfer the first voltage receives a high voltage VGH, a low voltage VGL [Park para 0024 and see Fig. 3]; and a second wire configured to transfer the second voltage the first voltage receives a high voltage VGH, a low voltage VGL [Park para 0024 and see Fig. 3];, wherein the first wire and the second wire are on a first side of the first transistor and the second transistor in a plan view. [Park see Fig. 2] The Office note as that both transistors are inside each stage and that the wires run to the left of each stage;
PNG
media_image1.png
602
825
media_image1.png
Greyscale
PNG
media_image2.png
317
565
media_image2.png
Greyscale
Regarding claim 22 Park teaches everything above see claim 21 in addition Park teaches further comprising: a third wire for transferring the first clock signal and on the first side of the first transistor and the second transistor. wire extending from line SCK1 to CK1 input [Park see Fig. 2]
Regarding claim 23 Park teaches everything above see claim 22 in addition Park teaches further comprising: a fourth wire for transferring the second clock signal and on the first side of the first transistor and the second transistor. wire extending from line SCK3 to CK3 input [Park see Fig. 2]
Regarding claim 24 Park teaches everything above see claim 23, in addition Park teaches wherein the first wire is between the third wire and the first and second transistor. M1 & M3 are between and VGHT and CLK1 [Park see Fig. 3]
Regarding claim 38 Park teaches a display device comprising: a scan driver a scan driver [Park para 0051] for generating a plurality of scan signals The display signal lines S1-Sn and D1-Dm include a plurality of scan lines S1-Sn for transmitting scan signals (referred to as "gate signals") and a plurality of data lines D1-Dm for transmitting data signals. [Park para 0054]; and a plurality of pixels for receiving a plurality of data voltages according to the plurality of scan signals, display signal lines S1-Sn and D1-Dm and a plurality of pixels PX connected thereto [Park para 0053] wherein the scan driver comprises: a plurality of unit scan driving circuits, the scan driver 200 of FIG. 1 includes a plurality of stages ST1-STn [Park para 0060 and see Fig. 2] at least one of the plurality of unit scan driving circuits comprising: a first transistor configured to receive an input signal in response to a first clock signal and output a second clock signal based on an enable level of the input signal The first transistor is connected between a first control terminal supplied with a voltage of a first level or a second level and an output terminal for outputting a scan signal having a voltage according to the voltage of the first control terminal, and the first transistor has a gate connected to a first node. [Park para 0024 and see Fig. 3]; a second transistor electrically connected between the first transistor and a first voltage; a third transistor electrically connected between a gate of the second transistor and a second voltage The third transistor is connected to a first voltage terminal supplied with a first voltage and the output terminal, and the first transistor has a gate connected to a second node [Park para 0024 and see Fig. 3]; a first wire configured to transfer the first voltage the first voltage receives a high voltage VGH, a low voltage VGL [Park para 0024 and see Fig. 3]; and a second wire configured to transfer the second voltage, wherein the first wire and the second wire are on a first side of the first transistor and the second transistor in a plan view. [Park see Fig. 2] The Office note as that both transistors are inside each stage and that the wires run to the left of each stage.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT J MICHAUD whose telephone number is (571)270-3981. The examiner can normally be reached 8:30 - 5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached on 571-272-7603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERT J MICHAUD/Examiner, Art Unit 2622
1 https://www.merriam-webster.com/dictionary/plan%20view