DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7 January 2026 has been entered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed 7 January 2026 have been fully considered but they are not persuasive.
On page 6 of the response the applicant argues amended claim 1, which recites “wherein the constant level of the gate-on voltage before the gate start signal is applied during the blank period is higher than a level of the gate-on voltage applied to the first gate line” with respect to Figure 4 of Song, stating that Song shows a level lower than that of gate-on voltage applied to a first gate line.
However, in response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Song et al. disclose of a constant level and Lee discloses a level of the gate-on voltage before the gate start signal is applied is higher than a level of the gate-on voltage applied to the first gate line. MPEP § 2141 III., which provides the rationales to support rejections under 35 U.S.C. 103, specifically (E) "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success. See also MPEP § 2143 I.E. Thus, based upon the teachings of references and the “obvious to try” rationale, the combination of references still suggest the amended limitations as claimed as explained in the rejection below.
Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak et al. (US 2016/0343341) in view of Lee (US 2008/0170064) and further in view of Song et al. (US 2013/0038587).
Regarding claim 1, Kwak et al. disclose a display device (Figure 1 and paragraph [0034]) comprising:
a display panel (Figure 1, 110) including a plurality of pixels (Figure 1, PX), and a plurality of gate lines (Figure 1, GL1-GLn) and a plurality of data lines connected to the plurality of pixels (Figure 1, DL1-DLm);
a gate driver applying a gate signal to the plurality of gate lines (Figure 1, 144 is a gate driver that applies a gate signal to GL1-GLn);
a data driver applying a data signal to the plurality of data lines (Figure 1, 130 is a data driver that applies a data signal to DL1-DLm); and
a circuit board including a voltage provider and a signal channel connecting the voltage provider to the gate driver (Figure 1, 142 is a voltage provider with a signal channel to provide VON and VOFF to the gate driver 144. Official Notice is taken that the circuits (ICs) would clearly be provided on a circuit board.),
wherein the gate driver receives, through the signal channel, a gate-on voltage that is gradually changed within one frame (Figure 1, VON is a gate-on voltage. Figure 8, S850 and Figure 7 and paragraph [0092], for example.) and a kickback voltage that is gradually changed within one frame from the voltage provider (Figure 8, S830 and Figure 7 and paragraph [0092], for example.), and applies the gate-on voltage and the kickback voltage to the plurality of gate lines (Figure 7 and paragraphs [0098]-[0099].), and
wherein the gate-on voltage gradually changes and is applied to the plurality of gate lines including a first gate line having a shortest distance through which the gate signal is applied and a n-th gate line, where n is an integer greater than one, having a longest distance through which the gate signal is applied (Figure 7 and paragraphs [0098]-[0099].).
Kwak et al. fail to teach wherein the gate-on voltage gradually increases and is applied to the plurality of gate lines including a first gate line having a shortest distance through which the gate signal is applied and a n-th gate line, where n is an integer greater than one, having a longest distance through which the gate signal is applied, wherein a level of the gate-on voltage gradually increases during an active period within one frame, and a level of the gate-on voltage before the gate start signal is applied is higher than a level of the gate-on voltage applied to the first gate line.
Lee discloses a display device comprising:
a voltage provider (Figure 5) configured to generate a gate-on voltage that is gradually changed in one frame (Paragraph [0043] and Figure 7), wherein the gate-on voltage gradually increase and is applied to the plurality of gate lines including a first gate line having a shortest distance through which the gate signal is applied and a n-th gate line, where n is an integer greater than one, having a longest distance through which the gate signal is applied, and a level of the gate-on voltage gradually increases during an active period within one frame. (Paragraph [0043] and Figure 7, which shows that VON gradually increases during an active frame within one frame, i.e. increases from “shortest distance” to “longest distance”), and
a level of the gate-on voltage before the gate start signal is applied is higher than a level of the gate-on voltage applied to the first gate line (Figure 7 shows that VON is the highest before the start signal is applied.).
Therefore, it would have been obvious to “one of ordinary skill” in the art before the effective filing date of the claimed invention to use the changing gate-on voltage teachings of Lee and apply them to the gate-on voltage taught by Kwak et al. such that the gate-on voltage of Kwak et al. gradually increase and is applied to the plurality of gate lines from one of the plurality of gate lines having a shortest distance in which the gate signal is applied to one of the plurality of gate lines having a longest distance in which the gate signal is applied. The motivation to combine would have been in order to substantially prevent variations in brightness between the top and bottom of an LCD panel (See Lee, paragraph [0008].).
Kwak et al. and Lee fail to explicitly teach of a blank period, and therefore fail to teach that each of the gate-on voltage and the kickback voltage have a constant level before a gate start signal is applied during a blank period.
Song et al. disclose a display device comprising a blank period, wherein the voltages of all signals have a constant level before a gate start signal is applied during a blank period (Figure 4 shows a blank period VB, wherein the voltages of all of the signals, CKV1, CVK2, GV1, GV2…GVn, have a constant level during the blank period before a gate start signal STV1 is applied.).
Hence the prior art includes each element claimed although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of the actual combination of the elements in a single prior art reference. In combination, the combination of Kwak et al. and Lee performs the same function as it does separately of providing a gate-on and kickback voltage during an active period, and Song et al. performs the same function as it does separately of providing constant voltage levels of signals during a blank period.
Therefore, one of ordinary skill in the art before the effective filing date of the claimed invention could have combined the elements as claimed by known methods, and that in combination, each element merely performed the same function as it does separately. The results of the combination would have been predictable and resulted in each of the gate-on voltage and the kickback voltage having a constant level before a gate start signal is applied during a blank period.
Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
While Song et al. fail to explicitly teach wherein the constant level of the gate-on voltage before the gate start signal is applied during the blank period is higher than a level of the gate-on voltage applied to the first gate line, Lee already discloses that the level of the gate-on voltage before the gate start signal is applied is higher than a level of the gate-on voltage applied to the first gate line (See above). Therefore, before the effective filing date of the claimed invention, there had been a recognized problem or need in the art to provide voltage levels during a blanking period, in which the display is not driven, to ensure synchronization and ovoid onscreen tearing artifacts. There were a finite number of identified and predictable potential solutions to the recognized need or problem which were to provide either the low voltage, the high voltage or a voltage in-between. One of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success since these voltage levels are already available within the display device, where using the gate high voltage as the constant level would have been obvious since the voltage level of the gate-on voltage would already be “high” after the gradual increase during the display period in Figure 7 of Lee. Therefore, the claimed subject matter would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention.
Regarding claim 2, Kwak et al., Lee and Song et al. disclose the display device of claim 1, wherein a same amount of the kickback voltage is applied to the plurality of gate lines (Kwak et al.: Figures 6A and 6B show that the same amount is applied, just the slew rate is changed.).
Regarding claim 3, Kwak et al., Lee and Song et al. disclose the display device of claim 1,
a kickback time in which the kickback voltage is applied is different for at least one of the plurality of gate lines (Kwak et al.: Figures 6A-6B, for example, show the kickback time is “different” between VGOUT1 and VGOUTn.).
the kickback time gradually increases or decreases from the first gate line to the n-th gate line (Kwak et al.: Figures 6A-6B and paragraph [0086].).
Regarding claim 4, Kwak et al., Lee and Song et al. disclose the display device of claim 3, wherein a change amount of the kickback time is adjustable (Kwak et al.: Figures 6A-6B and paragraph [0086].).
Conclusion
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/STEPHEN G SHERMAN/Primary Examiner, Art Unit 2621
9 March 2026