DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over Nishimori et al. (U.S. Patent Application Publication No. 2014/0151748) in view of Wong (U.S. Patent No. 11,721,729).
Regarding claim 1, Nishimori discloses a nitride semiconductor device, comprising:
an electron transit layer composed of a nitride semiconductor (Fig. 3B, element 3; [0027], lines 1-2);
an electron supply layer composed of a nitride semiconductor having a larger band gap than the electron transit layer and disposed on the electron transit layer to generate two-dimensional electron gas in the electron transit layer (Fig. 3B, element 4; [0027], lines 1-2, [0031], lines 1-4, layer 4 contains Al thus has larger band gap than the electron transit layer 3. Layer 4 disposed on the electron transit layer 3 to generate 2DEG in the electron transit layer 3);
a gate layer composed of a nitride semiconductor containing acceptor impurities and disposed on the electron supply layer (Fig. 3B, element 5a; [0028], last lines, p-type semiconductor containing acceptor impurities);
a gate electrode contacting the gate layer (Fig. 3B, element 11; [0040], lines 1-2); and
a source electrode and a drain electrode that are electrically connected to the two-dimensional electron gas (Fig. 3B, elements 8 and 9; [0042], lines 2-3).
Nishimori does not explicitly disclose the gate layer includes a trench that is recessed from an upper surface of the gate layer in a region contacting the gate electrode, the trench includes a trench open end, a trench bottom surface, and a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end.
Wong discloses
an under-gate layer includes a trench that is recessed from an upper surface of the under-gate layer in a region contacting a gate electrode (Fig. 1B, element 20i, column 9, lines 24-25),
the trench includes
a trench open end (Fig. 1B),
a trench bottom surface (Fig. 1B), and
a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end (Fig. 1B).
PNG
media_image1.png
724
858
media_image1.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Nishimori in view of Wong to include in the gate layer a trench that is recessed from an upper surface of the gate layer in a region contacting the gate electrode, the trench includes a trench open end, a trench bottom surface, and a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end, in order to reduce contact resistance.
Regarding claim 2, Wong discloses
the trench open end includes a first edge and a second edge that face each other in a first direction (Fig. 1B),
the trench has a trench width corresponding to a distance between the first edge and the second edge in the first direction (Fig. 1B),
the gate electrode has a gate electrode length in the first direction (Fig. 1B), and
the trench width is less than or equal to the gate electrode length (Fig. 1B).
PNG
media_image2.png
732
883
media_image2.png
Greyscale
Regarding claim 3, Wong discloses
the gate electrode includes
a lower electrode portion filling the trench (Fig. 1B, portion of electrode 20 inside layer 14), and
an upper electrode portion formed integrally with the lower electrode portion and located upward from an upper surface position of the gate layer (Fig. 1B, portion of electrode 20 above layer 14), and
the upper electrode portion includes a side surface that is flatly continuous with an outer surface of the lower electrode portion at where the trench open end is located (Fig. 1B, sidewall surfaces of electrode 20).
Regarding claim 4, Wong discloses
the gate electrode includes
a lower electrode portion filling the trench (Fig. 1B, portion of electrode 20 inside layer 14), and
an upper electrode portion formed integrally with the lower electrode portion and located upward from an upper surface position of the gate layer (Fig. 1B, portion of electrode 20 above layer 14), and
the upper electrode portion includes a projection projecting sideways from the trench open end along the upper surface of the gate layer (Fig. 1B).
Regarding claim 5, Wong discloses the projection projects sideways from the trench open end along the upper surface of the gate layer over a projection width that is less than or equal to a depth of the trench (Fig. 1B).
Regarding claim 6, Wong discloses the projection projects sideways from the trench open end along the upper surface of the gate layer over a projection width that is greater than 0 nm (Fig. 3B). Wong does not specify an upper limit of the range. However, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the projection projects sideways from the trench open end along the upper surface of the gate layer over a projection width that is less than or equal to 100 nm in order to reduce footprint, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 7, Wong discloses the trench includes a trench wall surface connecting the trench open end and the curved surface (Fig. 1B).
Regarding claim 8, Wong discloses the trench wall surface includes an inclined surface (Fig. 1B).
Regarding claim 9, Wong discloses the inclined surface has an inclination angle of 30° or greater and 60° or less (Fig. 1B).
Regarding claim 10, Wong discloses the trench wall surface includes a vertical surface (Fig. 1B).
Regarding claim 11, Wong discloses the trench has a depth (Fig. 1B). Wong is silent about a dimension range, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure the trench having a depth of 10 nm or greater and 50 nm or less in order to obtain a desired contact resistance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 12, Wong discloses the curved surface has a radius of curvature (Fig. 1B). Wong is silent about a dimension range, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a radius of curvature of 10 nm or greater and 30 nm or less in order to avoid voids being formed, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding claim 13, Nishimori discloses
the electron transit layer is a GaN layer (Fig. 3B, layer 3 is GaN),
the electron supply layer is an AlGaN layer (Fig. 3B, layer 4 is AlGaN), and
the gate layer is a GaN layer containing the acceptor impurities (Fig. 3B, layer 5a is p-GaN, p-type impurities are acceptor impurities).
Pertinent Art
For the benefits of the Applicant, US-9666664-B2, US-20140092638-A1, US-7388236-B2, US-9601608-B2, US-7859021-B2, US-10322599-B1, US-8853666-B2, US-8791505-B2, US-8114717-B2, and US-9099351-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. In particular, the references fail to disclose “the gate layer includes a trench that is recessed from an upper surface of the gate layer in a region contacting the gate electrode, the trench includes a trench open end, a trench bottom surface, and a curved surface continuous with the trench bottom surface and curved from the trench bottom surface toward the trench open end.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VU A VU/Primary Examiner, Art Unit 2897
Prosecution Insights