Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
1. Claims 9-10 & 12 objected to because of the following informalities:
a. Per claim 9-10, line 1, change “the plurality of heat dissipation parts” to –a plurality of heat dissipation parts--.
b. Per claim 12, line 6, change “wherein the first the circuit board” to –wherein the first circuit board--.
. Appropriate correction is required.
Claim Rejections - 35 USC § 102
2. In the event that the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by OH et al. US2020/0152566.
Per claim 1 OH teaches a circuit board (see fig.1) comprising: a first insulating layer (210 & 220, see fig.1) having first (see fig.1, “top portion of 220”) and second surfaces (see fig.1, “bottom portion of 210”) opposing each other (see fig.1), and having a cavity (C1 & C2) recessed from the first surface (see fig.1); a first heat dissipation pattern (BP, see fig.1; [0055], “copper is a heat dissipation component, therefore the copper pattern is the first heat dissipation pattern”) disposed on the second surface of the first insulating layer (see fig.1); and a heat dissipation part (300; [0055]) connected to the first heat dissipation pattern (see fig.1), and protruding into the cavity by penetrating through the first insulating layer (see fig.1).
Per claim 2 OH et al. teaches the circuit board of claim 1, further comprising a second insulating layer (100) disposed on the second surface in a first direction to cover the first heat dissipation pattern and at least one circuit pattern layer (510, see fig.1), wherein the first insulating layer (210 & 220) includes an upper region overlapping the cavity in the first direction and a side region overlapping the cavity in a second direction perpendicular to the first direction, and the heat dissipation part protrudes from the upper region (see fig.1).
Per claim 3 OH et al. teaches the circuit board of claim 2, wherein the heat dissipation part (300) includes: a first part buried in the first insulating layer, and a second part extending from the first part and protruding from the upper region (see fig.1).
Per claim 4 OH et al. teaches the circuit board of claim 3, wherein the first insulating layer (210 & 220) has a groove in the upper region where the second part is disposed, and the groove surrounds the second part (see fig.1).
Per claim 5 OH et al. teaches the circuit board of claim 1, further comprising: a first pattern layer (BP, see fig.1) including the first heat dissipation pattern (BP) and a first circuit pattern layer (510) disposed around the first heat dissipation pattern (see fig.1), wherein the first heat dissipation pattern is connected to at least one other pattern layer (see fig.1).
Per claim 8 OH et al. teaches the circuit board of claim 1, wherein the heat dissipation part extends to be parallel to an edge of the cavity (see fig.1).
Per claim 9 OH et al. teaches the circuit board of claim 1, wherein the plurality of heat dissipation parts are provided, and the plurality of heat dissipation parts include portions aligned with each other in one direction (see fig.1).
Per claim 10 OH et al. teaches the circuit board of claim 1, wherein the plurality of heat dissipation parts are provided, and the plurality of heat dissipation parts are spaced apart from each other (see fig.1).
Per claim 11 OH et al. teaches the circuit board of claim 1, wherein the heat dissipation part includes copper ([0055]).
Allowable Subject matter
3. Claims 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 6, includes allowable subject matter because of the circuit board of claim 5, further comprising: a second heat dissipation pattern disposed on the first surface of the first insulating layer, Wherein the first heat dissipation pattern is connected to the second heat dissipation pattern.
Claim 7, includes allowable subject matter because of the circuit board of claim 5, further comprising: a second insulating layer disposed on the second surface in a first direction to cover at least one pattern layer including the first pattern layer; and a third heat dissipation pattern disposed on a third surface of the second insulating layer that opposes the second surface of the first insulating layer, wherein the first heat dissipation pattern is connected to the third heat dissipation pattern.
Claims 12 - 20 are allowable
Regarding Independent claim 12, patentability exists, at least in part, with the claimed combination of elements and features of: An electronic component package comprising: a first circuit board having a cavity in one surface; a second circuit board connected to the first circuit board; and an electronic component mounted on one surface of the second circuit board, and accommodated in the cavity, wherein the first the circuit board includes: a first insulating layer having first and second surfaces opposing each other, and having the cavity recessed from the first surface, a first heat dissipation pattern disposed on the second surface of the first insulating layer, and a heat dissipation part connected to the first heat dissipation pattern, and protruding into the cavity by penetrating through the first insulating layer.
Claims 13-20 depends on claim 12, therefore allowable for the same reason.
Email Communication
4. Applicant is encouraged to authorize the Examiner to communicate via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502, 502.05.
Conclusion
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. US2023/0292428 discloses a circuit board, comprising: a conductive metal layer, mainly configured to transmit an electronic signal; at least one insulating layer, connected to the conductive metal layer; at least one thermally conductive insulating layer, sandwiched between the conductive metal layer and the insulating layer.
KO US2012/0228007 discloses a printed circuit board, comprising: a core substrate including core circuit layers on both sides thereof; a first build-up layer formed on one side of the core substrate; a second build-up layer formed on the other side of the core substrate; and first and second protective layers formed on the first and second build-up layers.
Applicants are directed to consider additional pertinent prior are included on the Notice of References Cited (PTOL 892) attached herewith. The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply. Applicant, in preparing the response, should consider fully the entire reference as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL A MATEY whose telephone number is (571)270-5648. The examiner can normally be reached on Monday-Friday 9AM-6PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAYPRAKASH GANDHI can be reached on 5712723740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL A MATEY/Primary Examiner, Art Unit 2835
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