DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claim(s) 18-35 and 37-40 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 6/8/26.
Applicant's election with traverse of Species I, claims 1-17 and 36 in the reply filed on 6/8/26 is acknowledged. Applicant's arguments filed on 6/8/2026 have been fully considered but they are not persuasive. The arguments at page three (3) submit that all five Species share “the Special Feature (STF).” It is unknow that these STF may be. The arguments, in brief and saliently, seem to allege that “input/output of metadata between cores and the meta storage circuits is controlled on the basis of a column address. For one, and for example, claim 1 as originally filed does not seem to include “input/output of metadata between cores and the meta storage circuits.” The quoted portion seems to be directed to metadata transfers (I/O) between cores and meta storage circuit. While claim 1, relevantly requires: “when a meta write operation is performed, data that are received through an external line are stored in the plurality of memory cores … and metadata that are received through a meta line are stored in a meta storage circuit.” This differs significantly from the submission in the arguments. Furthermore, the arguments allege that “Each Species merely differs in the direction of the data/metadata flow.” To be known, Species I requires, in brief, a data and metadata write operation. Species II requires, in brief, a data and metadata read operation. Species III requires, in brief, when an internal meta write operation is performed, metadata is read out to memory core. Species IV requires, in brief, when an internal meta read operation is performed, metadata is written out from the core to meta storage. Species V requires subject matter not presented in any of the other Species, and it involves parallel-writes, test voltage etc. It is therefore found that the difference among the Species are not mere differences in the direction of the data/metadata flow. The Restriction/Election previously presented is still deemed proper and is therefore made FINAL.
Allowable Subject Matter
Claim(s) 10 and 14 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: when an internal meta write operation is performed, the metadata stored in the plurality of meta storage circuits are output to a read meta line based on the column address, and when the internal meta write operation is performed, the metadata that are received through the read meta line are stored in the plurality of memory cores based on the column address; while in regard to claim 14, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: when an internal meta read operation is performed, the metadata stored in the plurality of memory cores are output to a write meta line based on the column address, and when the internal meta read operation is performed, the metadata that are received through the write meta line are stored in the plurality of meta storage circuits based on the column address.
Claim(s) 11-13 and 15-17 depend from claim(s) 10 and 14 and as such are therefore objected for at least the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 6-8 and 36 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20250110643 to Ayyapureddi (“Ayya”).
As to claim 1, Ayya teaches A memory device (As found in at least FIGS. 1-2, at least [0012] and at least the Abstract) comprising: a plurality of memory cores (As found in at least FIG. 2: plurality of memory cores BANK0-7); and a plurality of meta storage circuits (As found in at least [0038]: data and metadata supplied to the data terminals DQ by the controller is provided along the data bus and written to memory cells in the memory array 218), each of the plurality of meta storage circuits corresponding to a different one of the plurality of memory cores (As found in at least [0038] and FIG. 2: for each BANK, data and metadata is stored); wherein, when a meta write operation is performed, data that are received through an external line are stored in the plurality of memory cores based on a column address (As found in at least [0038] and at least FIG. 2: write operation, data supplied to data lines DQ, based on column address and stored in at least one of BANK0-7), and metadata that are received through a meta line are stored in a meta storage circuit (As found in at least [0038] and at least FIG. 2: write operation, metadata supplied to data lines DQ, based on column address and stored in at least part of one of BANK0-7), among the plurality of meta storage circuits (At least one of BANK0-7), that is selected by the column address (As selected by column address, as found in at least [0038]).
As to claim 2, Ayya teaches wherein when the meta write operation is performed, a column selection signal is selected by the column address, and the data are stored in memory cells that belong to the plurality of memory cores and that are accessed by the selected column selection signal (As found in at least [0055]).
As to claim 3, Ayya teaches an input and output line driver configured to output the data to an internal line when the meta write operation is performed (As found in at least FIG. 2: I/O driver 222 to drive internal line); a write driver configured to output, to a local line, the data that are received through the internal line when the meta write operation is performed (As found in at least FIG. 2: ECC 220: receives from internal line and drives local line); and a column decoder configured to generate the column selection signal based on the column address when the meta write operation is performed (As found in at least FIG. 2: column decoder 210).
As to claim 6, Ayya teaches when a meta read operation is performed, the data stored in the plurality of memory cores are output to the external line based on the column address; and when the meta read operation is performed, the metadata stored in the meta storage circuit that is selected by the column address are output to the meta line (As found in at least [0014: The data and the metadata together represent information written to the memory by a controller and then also read from the memory by the controller; while at least [0035] teaches read operations based on column addresses).
As to claim 7, see rejection to at least claim 2.
As to claim 8, see rejection to at least claim 2; further, Ayya teaches a column decoder configured to generate the column selection signal based on the column address when the meta read operation is performed (As found in at least FIG. 2 and at least [0031]: column decoder 210); an input and output sense amplifier configured to receive, through a local line, the data that are output by the plurality of memory cores and output the data to an internal line (As found in at least FIG. 2 and at least [0032]: sense amplifier SAMP, local line LIO, outputs data), based on the column selection signal when the meta read operation is performed (As found in at least FIGS. 2-3: column selection signal CSn); and an input and output line driver configured to output, to the external line, the data that are received through the internal line when the meta read operation is performed (As found in at least FIG. 2: I/O).
As to claim 36, see rejection to at least claim 1; moreover, the method is inherently taught by the apparatus.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20250110643 to Ayyapureddi (“Ayya”) in view of KR 102497130 B1 A to Kim (“Kim”).
As to claim 4, at least Kim teaches wherein each of the meta storage circuits comprises a plurality of metadata drivers and a plurality of meta registers (As found in at least FIGS. 2-3: metadata driver 1140 and metadata register 1150 and/or 1160); wherein each of the plurality of metadata drivers corresponds to at least one meta register among the plurality of meta registers (As found in at least FIGS. 2-3); and wherein at least one of the plurality of metadata drivers and at least one of the plurality of meta registers are selected by a meta group signal (As found in at least FIG. 2: 1140 and 1150/1160 are selected by signaling as found in at least FIG. 2).
Ayya and Kim are analogous art because they are from the same field of endeavor, and/or are reasonably pertinent to the inventor’s problem to be solved: memory having metadata storage.
At the time of invention, it would have been obvious to a person of ordinary skill in the art to complement the teachings of Ayya as set forth in this Office action and as found in the reference with the relevant and complementary teachings of Kim also as set forth in this Office action and as found in the reference(s). The suggestion/motivation would have been obvious to one of ordinary skill in the art before the effective filing date of the present Application: Ayya teaches a memory device including metadata storage, Kim provides further teachings on the details of such metadata storage.
Therefore, it would have been obvious to combine Ayya with Kim to make the above modification.
As to claim 5, see rejection to at least claim 4: meta driver and meta register.
As to claim 9, see rejection to at least claim 4.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827
Prosecution Insights