DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-21 are pending in the application.
Examiner’s Note: The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS."
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/22/2024 was filed after the mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 10-13, 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta et al. US Pub. No. 20160377425 (“Gupta”) in view of Isao Yonekura et al. “Study of Contour Image Comparison Measurement for Photomask Patterns of 32 nm and Beyond”, 2009, (“Isao”).
Regarding claim 1, Gupta teaches a system comprising:
a controller comprising one or more processors configured to execute program instructions [See fig. 1 and 18], wherein the program instructions are configured to cause the one or more processors to:
acquire one or more images of features of a sample from a metrology sub-system;
[0009] One embodiment relates to a system configured to determine overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process. The system includes an output acquisition subsystem that includes at least an energy source and a detector. The energy source is configured to generate energy that is directed to a wafer. The detector is configured to detect energy from the wafer and to generate output responsive to the detected energy. First and second patterned features are printed on a level of the wafer with first and second patterning steps, respectively. The system also includes one or more computer subsystems configured for aligning a design for the level of the wafer to an image for the wafer generated from the output thereby aligning the design for the first patterned features to the first patterned features in the image thereby aligning all of the design for the level to the first patterned features.
[See further paragraph 28-33, 42: configured to acquire images of patterned features on the wafer]
acquire sample design data comprising design data shapes corresponding to the features of the sample; and
[0029] The terms “design” and “design data” as used herein generally refer to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations. The physical design may be stored in a data structure such as a graphical data stream (GDS) file, any other standard machine-readable file, any other suitable file known in the art, and a design database. A GDSII file is one of a class of files used for the representation of design layout data.
[0030] In some instances, simulated or acquired images from a wafer or reticle can be used as a proxy for the design. Image analysis can also be used as a proxy for design analysis. For example, polygons in the design may be extracted from an image of a design printed on a wafer and/or reticle, assuming that the image of the wafer and/or reticle is acquired with sufficient resolution to adequately image the polygons of the design. In addition, the “design” and “design data” described herein refers to information and data that is generated by semiconductor device designers in a design process and is therefore available for use in the embodiments described herein well in advance of printing of the design on any physical wafers.
Gupta further teaches measure overlay error as a positional shift (X/Y offset) between design and image, not area-based on-overlap.
[0033] One embodiment relates to a system configured to determine overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process. The wafer may include any wafer known in the art.
[0063] One example of how patterned features printed on a wafer can be different from patterned features as-designed is shown in FIGS. 4 and 5. In particular, FIG. 4 shows the portion of the design shown in FIG. 3 as the patterned features shown in FIG. 3 are designed while FIG. 5 shows the portion of the design shown in FIG. 3 as the patterned features shown in FIG. 3 may be printed on a wafer. More specifically, due to the inherent limitations of the tools, materials, and processes used to print the patterned features shown in portion 400 of the design, the patterned features will not necessarily be printed on the wafer as they are included in the design. For example, as shown in FIG. 5, instead of the patterned features in portion 400 having sharp, 90-degree corners as shown in the design, the features will have at least somewhat rounded corners. In addition, any of the features may have variations in dimensions such as width at various points across the features. Therefore, due to the differences between the patterned features as-designed and the patterned features as-printed, aligning information for a design to an image of patterned features on a wafer is not always a trivial process. However, as will be described further herein, the embodiments described herein can be used to align information for a design to an image of patterned features with substantially high accuracy which allows for determining relative overlay error with substantially high accuracy. [See further paragraph 61-64, 70-72].
Gupta does not teach perform one or more feature placement error (FPE) measurements based on areas of nonoverlap between shapes of the features in the one or more images and the design data shapes in the sample design data.
Isao teaches a method for measuring the differences in two patterns using contour data extracted from SEM images. Specifically, Isao teaches perform one or more feature placement error (FPE) measurements based on areas of nonoverlap between shapes of the features in the one or more images and the design data shapes in the sample design data [See fig. 1-2, 6, 8].
This function employs sub-pixel contour data extracted with high accuracy to quantify a slight difference by ΔCD and ΔArea. [ABSTRACT]
As LSI pattern complexity has persisted, requirements for photomask pattern miniaturization and accuracy have been tightened. Naturally, requirements for photomask pattern measurement precision have become more stringent. Measurement reproducibility of 0.2 nm (3σ) and below is required for 32 nm hp node in ITRS2008[1]. Moreover, not only one-dimensional but also two-dimensional quantification techniques are needed due to ever-elaborating pattern features. [page 1]
2.3 Uncertainty of the Contour Comparison Measurement
2.3.1 Concept of measurement uncertainty
The most common approach to quantify a defect is to compare a defective pattern with a non-defective pattern. A difference between reference and target pattern CDs is defined as a defect. Formula 1 is used for defining a defect. As indicated in Formula 2, the measurement uncertainty is expressed by the square root of the square sum of variability of reference and target pattern CDs. And Formula 3 expresses the variability of CDs is that corresponds to the variability of pattern edge positions. Therefore, the measurement uncertainty can be defined as the variation in positions of 4 edges.
With the Contour Comparison Measurement that we proposed, defects can be defined by differences in edge positions of reference and target patterns as indicated in Formula 4. It is necessary to consider position matching errors when overlapping a reference pattern and a target pattern. As expressed in Formula 5, in fact, the measurement uncertainty is defined by the square root of the square sum of the following variabilities: reference pattern edge positions, target pattern edge positions, and position matching errors. [Read further pages 4-5, 8]
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Gupta and Isao since they both are directed to semiconductor metrology. Specifically, using SEM images and design data (GDS) to characterize patterned features on a semiconductor wafer and address the problem of quantifying deviations between as-designed and as-fabrication patterns. Isao teachings of perform one or more feature placement error (FPE) measurements based on areas of nonoverlap between shapes of the features in the one or more images and the design data shapes in the sample design data would further improve the shift-based overly measurement of Gupta by providing a more comprehensive measurement of feature placement error.
Regarding claim 10, Gupta teaches the sample design data comprises polygon data associated with the features [See par. 29-30, 78-79].
Regarding claim 11, Gupta teaches a system [see fig. 1 and 18] comprising:
a metrology sub-system [10]; and
a controller [36] communicatively coupled to the metrology sub-system and comprising one or more processors configured to execute program instructions causing the one or more processors to:
acquire one or more images of features of a sample;
[0009] One embodiment relates to a system configured to determine overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process. The system includes an output acquisition subsystem that includes at least an energy source and a detector. The energy source is configured to generate energy that is directed to a wafer. The detector is configured to detect energy from the wafer and to generate output responsive to the detected energy. First and second patterned features are printed on a level of the wafer with first and second patterning steps, respectively. The system also includes one or more computer subsystems configured for aligning a design for the level of the wafer to an image for the wafer generated from the output thereby aligning the design for the first patterned features to the first patterned features in the image thereby aligning all of the design for the level to the first patterned features.
[See further paragraph 28-33, 42: configured to acquire images of patterned features on the wafer]
acquire sample design data comprising design data shapes corresponding to the features of the sample; and
[0029] The terms “design” and “design data” as used herein generally refer to the physical design (layout) of an IC and data derived from the physical design through complex simulation or simple geometric and Boolean operations. The physical design may be stored in a data structure such as a graphical data stream (GDS) file, any other standard machine-readable file, any other suitable file known in the art, and a design database. A GDSII file is one of a class of files used for the representation of design layout data.
[0030] In some instances, simulated or acquired images from a wafer or reticle can be used as a proxy for the design. Image analysis can also be used as a proxy for design analysis. For example, polygons in the design may be extracted from an image of a design printed on a wafer and/or reticle, assuming that the image of the wafer and/or reticle is acquired with sufficient resolution to adequately image the polygons of the design. In addition, the “design” and “design data” described herein refers to information and data that is generated by semiconductor device designers in a design process and is therefore available for use in the embodiments described herein well in advance of printing of the design on any physical wafers.
Gupta further teaches measure overlay error as a positional shift (X/Y offset) between design and image, not area-based on-overlap.
[0033] One embodiment relates to a system configured to determine overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process. The wafer may include any wafer known in the art.
[0063] One example of how patterned features printed on a wafer can be different from patterned features as-designed is shown in FIGS. 4 and 5. In particular, FIG. 4 shows the portion of the design shown in FIG. 3 as the patterned features shown in FIG. 3 are designed while FIG. 5 shows the portion of the design shown in FIG. 3 as the patterned features shown in FIG. 3 may be printed on a wafer. More specifically, due to the inherent limitations of the tools, materials, and processes used to print the patterned features shown in portion 400 of the design, the patterned features will not necessarily be printed on the wafer as they are included in the design. For example, as shown in FIG. 5, instead of the patterned features in portion 400 having sharp, 90-degree corners as shown in the design, the features will have at least somewhat rounded corners. In addition, any of the features may have variations in dimensions such as width at various points across the features. Therefore, due to the differences between the patterned features as-designed and the patterned features as-printed, aligning information for a design to an image of patterned features on a wafer is not always a trivial process. However, as will be described further herein, the embodiments described herein can be used to align information for a design to an image of patterned features with substantially high accuracy which allows for determining relative overlay error with substantially high accuracy. [See further paragraph 61-64, 70-72].
Gupta does not teach perform one or more feature placement error (FPE) measurements based on areas of nonoverlap between shapes of the features in the one or more images and the design data shapes in the sample design data.
Isao teaches a method for measuring the differences in two patterns using contour data extracted from SEM images. Specifically, Isao teaches perform one or more feature placement error (FPE) measurements based on areas of nonoverlap between shapes of the features in the one or more images and the design data shapes in the sample design data [See fig. 1-2, 6, 8].
This function employs sub-pixel contour data extracted with high accuracy to quantify a slight difference by ΔCD and ΔArea. [ABSTRACT]
As LSI pattern complexity has persisted, requirements for photomask pattern miniaturization and accuracy have been tightened. Naturally, requirements for photomask pattern measurement precision have become more stringent. Measurement reproducibility of 0.2 nm (3σ) and below is required for 32 nm hp node in ITRS2008[1]. Moreover, not only one-dimensional but also two-dimensional quantification techniques are needed due to ever-elaborating pattern features. [page 1]
2.3 Uncertainty of the Contour Comparison Measurement
2.3.1 Concept of measurement uncertainty
The most common approach to quantify a defect is to compare a defective pattern with a non-defective pattern. A difference between reference and target pattern CDs is defined as a defect. Formula 1 is used for defining a defect. As indicated in Formula 2, the measurement uncertainty is expressed by the square root of the square sum of variability of reference and target pattern CDs. And Formula 3 expresses the variability of CDs is that corresponds to the variability of pattern edge positions. Therefore, the measurement uncertainty can be defined as the variation in positions of 4 edges.
With the Contour Comparison Measurement that we proposed, defects can be defined by differences in edge positions of reference and target patterns as indicated in Formula 4. It is necessary to consider position matching errors when overlapping a reference pattern and a target pattern. As expressed in Formula 5, in fact, the measurement uncertainty is defined by the square root of the square sum of the following variabilities: reference pattern edge positions, target pattern edge positions, and position matching errors. [Read further pages 4-5, 8]
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to combine the teachings of Gupta and Isao since they both are directed to semiconductor metrology. Specifically, using SEM images and design data (GDS) to characterize patterned features on a semiconductor wafer and address the problem of quantifying deviations between as-designed and as-fabrication patterns. Isao teachings of perform one or more feature placement error (FPE) measurements based on areas of nonoverlap between shapes of the features in the one or more images and the design data shapes in the sample design data would further improve the shift-based overly measurement of Gupta by providing a more comprehensive measurement of feature placement error.
Regarding claim 12, Gupta teaches the metrology sub-system comprises an electron beam metrology tool [See fig. 1].
Regarding claim 13, it is directed the method to implement the system as set forth in claim 1. Therefore, it is rejected on the same basis as set forth hereinabove.
Regarding claim 20, Gupta teaches acquiring the one or more images is performed via a metrology sub-system comprising an electron beam metrology tool [See fig. 1].
Regarding claim 21, Gupta teaches the sample design data comprises polygon data of the features [See par. 29-30, 78-79].
Claim(s) 2-3, 7, 14-15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta/Isao as applied to claim 1 or 13 above, and further in view of Hsu et al. US Pub. No. 2017/0082927 (“Hsu”).
Regarding claim 2, Gupta/Isao teaches perform one or more feature placement error. Gupta/Isao does not teach perform one or more simulated FPE measurements based on simulated adjustments to at least one of: X-direction offset, Y-direction offset, focus, light source dose, aberration correction, or critical dimension size.
Hsu teaches perform one or more feature placement error. Gupta/Isao does not teach perform one or more simulated PE measurements based on simulated adjustments to at least one of: X-direction offset, Y-direction offset, focus, light source dose, aberration correction, or critical dimension size [par. 65, 71, 98-103, 105 - PDEs may be measured from the simulated or actual position of a post-OPC pattern to its intended position. During the process of OPC, edges or part of edges in individual patterns in a design layout may be shifted].
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Gupta/Isao’s FPE measurement process to include more simulated PE measurements based on simulated adjustments to at least one of: X-direction offset, Y-direction offset, focus, light source dose, aberration correction, or critical dimension size of Hsu. The motivation for doing so would have been to reduce computational and manufacturing overhead, allow rapid evaluation of multiple parameter combinations, and improve optimization efficiency.
Regarding claim 3, Hsu teaches determine one or more approximate FPE measurements from the one or more simulated FPE measurements based on a cost function [See par. 71-80].
Regarding claim 7, Hsu teaches at least one of the one or more images of the features of the sample is configured to be acquired at after-develop inspection (ADI) [See par. 4 - After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the transferred circuit pattern].
Regarding claims 14-15, and 17, see discussion in claims 2-3, and 7 above.
Regarding claim 16,
Claim(s) 8-9, 16, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gupta/Isao as applied to claim 1 or 13 above, and further in view of Pandev et al. US Pub. No. 2022/0357673 (“Pandev”).
Regarding claim 8, Gupta/Isao does not expressly teach at least one of the one or more images of the features of the sample is configured to be acquired at after-clean inspection (ACI).
Pandev teaches the one or more images of the features of the sample is configured to be acquired at after-clean inspection (ACI). In particular, Pandev teaches that an overly metrology tool may obtain measurement data following various fabrication stages, including one or more cleaning steps, thereby performing after-clean inspection (ACI) measurements. Pandev further explains that metrology images acquired after cleaning are used for overly measurement and process control [See Abstract, par. 47-51].
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the system of Gupta/Isao so that at least one of the one or more images of the features of the sample is configured to be acquired at after-clean inspection (ACI) as taught by Pandev. The motivation for doing so would have allowed the metrology system of Gupta/Isao to inspect wafer features after post-processing cleaning operations, thereby improving process monitoring and overly measurement accuracy at additional manufacturing stages.
Regarding claim 9, Pandev further teaches render the sample design data based on metrology calibration parameters determined from the one or more images to generate rendered sample design data [par. 4-5, 33-38].
Regarding claim 16, Pandev teaches this overlay data may then be used for various purposes including, but not limited to, diagnostic information of the lithography tools or for the generation of process-control correctables. For instance, overlay data for samples in a lot may be used to generate feedback correctables for controlling the lithographic exposure of subsequent samples in the same lot… overlay data for samples in a lot may be used to generate feed-forward correctables [par. 43]. Therefore, Gupta/Isao in view of Pandev teaches transmitting data in a feed forward or feedback loop to a fabrication tool based on the one or more adjusted FPE measurements.
Regarding claims 18-19, see discussion in claims 8-9 above.
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter Claims 4-6 are considered allowable since, when reading the claims in light of the specification, none of the references of record alone or in combination disclose or suggest the combination of subject matter specified in the dependent claim(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Pub. No. 2024/0427967 to Ma et al. teach a Model-based OPC then performs simulation to predict the printed image. The distances between the target image and the simulated image are referred to as edge placement error (EPE). Based on edge placement errors, the edge fragments are individually moved or adjusted. The image that would be produced by a mask using the displaced edge fragments is simulated, and the new simulated image is compared with the target image, and the edge placement error for each edge fragment is again computed. This process of moving the edge fragments, simulating the image that would be produced using the moved edge fragments, and comparing the simulated image to the target image may be repeated for a number of times to ensure the simulated image for the resulting mask to reproduce the target image as much as possible.
US Pub. No. 2024/0112322 to Nishihata et al. an image to be measured of a sample that is captured by a microscope is acquired, a first degree that indicates a degree in which the second layer (upper layer) of the sample transmits the first layer (lower layer) is acquired, a first layer template image and a second layer template image indicating pattern shapes of the first layer and the second layer are acquired, pattern matching processing of the second layer is performed based on the second layer template image and the image to be measured to acquire a second position deviation amount related to the second layer and an area recognized as the second layer on the image to be measured, a consideration range of the image to be measured in pattern matching processing of the first layer is determined based on the first degree and the area recognized as the second layer, pattern matching processing of the first layer is performed based on the first layer consideration range, the first layer template image, and the image to be measured to acquire a first position deviation amount related to the first layer and an area recognized as the first layer on the image to be measured, and an overlay is measured based on the second position deviation amount and the first position deviation amount.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT HUY TRAN whose telephone number is (571)272-7210. The examiner can normally be reached M-F 7:00-4:00.
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VINCENT H TRAN
Primary Examiner
Art Unit 2115
/VINCENT H TRAN/Primary Examiner, Art Unit 2115
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