DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 09/25/2024. Claims 1-20 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 11/13/2024.
Oath/Declaration
The oath or declaration filed on 09/25/2024 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MA et al (US 2022/0037335 A1; hereafter MA).
PNG
media_image1.png
681
512
media_image1.png
Greyscale
Regarding claim 1. MA discloses a semiconductor device (Fig [1-2]) comprising:
a substrate (Fig [1-2], substrate 100, Para [ 0023]) including a first active region (“The active regions ACT may be defined by an element separation film (110 of FIG. 2)”, Para [0023]);
a bit line (Fig [1-2], bit line structures 135_1, Para [0041]) arranged on the substrate (Fig [1-2], substrate 100, Para [0023]), crossing the first active region (Fig [1-2], active regions ACT, Para [ 0023]), and extending in a first direction parallel to a top surface of the substrate (Fig [1-2], substrate 100, Para [ 0023]);
a bit line contact (Fig [1-2], bit line contact 136, Para [ 0047]) arranged between the bit line (bit line structures 135_1, Para [0041]) and the first active region (Fig [1-2], active regions ACT), and arranged in a bit line contact hole (first trench 136t, as shown in figure 5 ), the bit line contact hole (first trench 136t, as shown in figure 5 ) extending into the substrate (Fig [1-2], substrate 100, Para [ 0023]);
a bit line contact spacer (spacers 155, Para [0057]) arranged on a sidewall of the bit line contact (Fig [1-2], bit line contact 136, Para [0047]) within the bit line contact hole (first trench 136t, as shown in figure 5);
a bit line spacer (Fig [1-2], spacers 153, Para [0057]) arranged on a sidewall of the bit line (bit line structures 135_1, Para [0041]);
an anti-oxidation layer (Fig [1-2], spacers 154, Para [0057]) arranged between the sidewall of the bit line (Fig [1-2], bit line structures 135_1, Para [0041]) and the bit line spacer (spacers 153, Para [0057]) and between the sidewall of the bit line contact (bit line contact 136, Para [ 0047]) and the bit line spacer (spacers 155, Para [ 0057]); and
a buried contact (Fig [1-2], storage contact 140, Para [ 0035]) arranged in a buried contact hole (Fig [1-2], second trench 140t, Para [ 0058]), passing through the bit line contact spacer (Fig [1-2], spacers 155, Para [ 0057]), and contacting the first active region (“The active regions ACT may be defined by an element separation film (110 of FIG. 2)”, Para [0023]), wherein the anti-oxidation layer (spacers 154, Para [ 0057]) includes a silicon-containing material, and the silicon-containing material includes SiOx, where 0 < x ≦ 2 (spacers 154, Para [ 0057]).
Regarding claim 2. MA discloses the semiconductor device of claim 1, MA further discloses wherein the bit line comprises an upper conductive layer including a metal material (Fig [1-2], conductive film 133, Para [ 0048]), the anti-oxidation layer (spacers 154, Para [ 0057]) includes a first portion arranged on a sidewall of the upper conductive layer ( Fig [1-2], conductive film 133, Para [ 0048]), and the first portion comprises silicon oxide (SiO2).
Regarding claim 3. MA discloses the semiconductor device of claim 1, MA further discloses wherein the silicon-containing material further comprises impurities, and the impurities comprise at least one of carbon or chlorine (spacers 154, Para [ 0057]).
Regarding claim 13. MA discloses a semiconductor device comprising:
a substrate (Fig [1-2], substrate 100, Para [ 0023]) including a plurality of first active regions (“The active regions ACT may be defined by an element separation film (110 of FIG. 2)”, Para [0023]);
a plurality of bit lines (Fig [1-2], bit line structures 135_1 and 135_2, Para [0053]) placed on the substrate (Fig [1-2], substrate 100, Para [0023]), crossing the plurality of first active regions (Fig [1-2], active regions ACT), and extending in a first direction parallel to a top surface of the substrate (Fig [1-2], substrate 100, Para [ 0023]);
a bit line contact (Fig [1-2], bit line contact 136, Para [ 0047]) arranged between a first bit line among the plurality of bit lines (Fig [1-2], bit line structures 135_1 and 135_2, Para [0053]) and a first active region among the plurality of first active regions (active regions ACT), corresponding to the first bit line (Fig [1-2], bit line structures 135_1), and arranged within a bit line contact hole (first trench 136t, as shown in figure 5 ), the bit line contact hole (first trench 136t, as shown in figure 5 ) extending into the substrate (Fig [1-2], substrate 100, Para [ 0023]);
an anti-oxidation layer (spacers 154, Para [0057]) including a first portion arranged on a sidewall of the first bit line (Fig [1-2], bit line structures 135_1, Para [0041]) and a second portion arranged on an inner wall of the bit line contact hole (first trench 136t, as shown in figure 5);
a bit line contact spacer (Fig [1-2], spacers 153, Para [0057]) arranged on the second portion of the anti-oxidation layer (spacers 154, Para [0057]) and filling the bit line contact hole (Fig [1-2], first trench 136t, as shown in figure 5); and
a buried contact (Fig [1-2], storage contact 140, Para [ 0035]) arranged between the first bit line and a second bit line (Fig [1-2], bit line structures 135_1 and 135_2, Para [0053]) adjacent to the first bit line among the plurality of bit lines (Fig [1-2], bit line structures 135_1 and 135_2, Para [0053]), arranged in a buried contact hole (Fig [1-2], second trench 140t, Para [ 0058]), passing through the bit line contact spacer (Fig [1-2], spacers 153, Para [ 0057]) and the second portion of the anti-oxidation layer (Fig [1-2], spacers 154, Para [ 0057]), and contacting the first active region ( active regions ACT, Para [0023]), wherein the anti-oxidation layer (spacers 154, Para [ 0057]) includes a silicon-containing material, and the silicon-containing material includes SiOx, where 0 < x ≦ 2 (spacers 154, Para [ 0057]).
Regarding claim 14. MA discloses the semiconductor device of claim 13, MA further discloses wherein the first portion of the anti-oxidation layer (Fig [1-2], spacers 154, Para [0057]) includes silicon oxide (SiO2).
Regarding claim 15. MA discloses the semiconductor device of claim 13, MA further discloses wherein the silicon-containing material further comprises impurities, and the impurities comprise at least one of carbon or chlorine (spacers 154, Para [ 0057]).
Allowable Subject Matter
Claims 4-12 and 16-18 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following are the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 4. wherein the anti-oxidation layer includes a second portion arranged on an inner wall of the bit line contact hole, and the bit line contact spacer comprises: an insulating liner arranged on the inner wall of the bit line contact hole, and arranged on the second portion of the anti-oxidation layer; and a buried spacer arranged on the inner wall of the bit line contact hole, and arranged on the insulating liner.
Claims 5-8 are objected based on the dependency of claim 4.
Regarding claim 9. wherein the bit line spacer comprises:
a first spacer layer arranged on a sidewall of the anti-oxidation layer and including silicon oxide; and a second spacer layer arranged on a sidewall of the first spacer layer and including silicon nitride.
Claims 10-12 are objected based on the dependency of claim 9.
Regarding claim 16. wherein the bit line contact spacer comprises: an insulating liner arranged on the inner wall of the bit line contact hole, and arranged on the second portion of the anti-oxidation layer; and a buried spacer arranged on the inner wall of the bit line contact hole, and arranged on the insulating liner.
Claims 17-18 are objected based on the dependency of claim 16.
Claims 19-20 are allowed.
The following are the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
a buried contact arranged between the first bit line and a second bit line adjacent to the first bit line among the plurality of bit lines, arranged in a buried contact hole, passing through the bit line contact spacer and the second portion of the anti-oxidation layer, and contacting the first active region; a bit line spacer arranged on a sidewall of the first bit line, the bit line spacer including a first spacer layer arranged on a sidewall of the first portion of the anti-oxidation layer and including silicon oxide, and a second spacer layer arranged on a sidewall of the first spacer layer and including silicon nitride; and a landing pad arranged on the buried contact, wherein the anti-oxidation layer includes a silicon-containing material, and the silicon-containing material includes SiOx, where 0 < x ≦ 2, and the first portion of the anti-oxidation layer includes silicon oxide (SiO2), as recited in claim 19.
Claim 20 is allowed based on the dependency of claim 19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Prosecution Insights