DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The Information Disclosure Statement filed on 09/25/2024 has been considered.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12136952. Although the claims at issue are not identical, they are not patentably distinct from each other as reproduced below.
Claim 1 of 18/896335
Claims 1,2 and 5 U.S. Patent No. 12136952
A co-packaged integrated optoelectronic module, comprising:
A co-packaged integrated optoelectronic module, comprising:
an optoelectronic submodule, comprising:
an optoelectronic submodule, comprising:
a digital signal processing chip configured to convert an electrical analog signal, which is received, into an electrical digital signal, and process the electrical digital signal to output a high-speed digital signal;
a digital signal processing chip configured to convert an electrical analog signal, which is received, into an electrical digital signal, and process the electrical digital signal to output a high-speed digital signal;
an optoelectronic signal analog conversion chip connected to the digital signal processing chip and configured to convert an optical analog signal into the electrical analog signal to the digital signal processing chip; and
an optoelectronic signal analog conversion chip connected to the digital signal processing chip and configured to convert an optical analog signal into the electrical analog signal to the digital signal processing chip; and
an optical transceiver chip connected to the optoelectronic signal analog conversion chip and configured to receive and transmit the optical analog signal to the optoelectronic signal analog conversion chip, and transmit another optical analog signal;
an optical transceiver chip connected to the optoelectronic signal analog conversion chip and configured to receive and transmit the optical analog signal to the optoelectronic signal analog conversion chip, and transmit another optical analog signal;
a slave microprocessor connected to the optoelectronic submodule and configured to monitor operation of the optoelectronic submodule;
a slave microprocessor connected to the optoelectronic submodule and configured to monitor operation of the optoelectronic submodule;
a master microprocessor connected to the optoelectronic submodule and configured to process a low-speed digital signal transmitted from the co-packaged integrated optoelectronic module to the outside, monitor operation of the co-packaged integrated optoelectronic module, and perform initialization of the co-packaged integrated optoelectronic module;
a master microprocessor connected to the optoelectronic submodule and configured to process a low-speed digital signal transmitted from the co-packaged integrated optoelectronic module to the outside, monitor operation of the co-packaged integrated optoelectronic module, and perform initialization of the co-packaged integrated optoelectronic module;
a carrier board, wherein the optoelectronic submodule, the slave microprocessor and the master microprocessor are disposed on and electrically connected to the carrier board; and
a carrier board, wherein the optoelectronic submodule, the slave microprocessor and the master microprocessor are disposed on and electrically connected to the carrier board; and
a light source unit connected to the optical transceiver chip and the slave microprocessor and configured to output another optical analog signal to the optical transceiver chip for transmission based on a control signal from the slave microprocessor;
a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor; wherein the slave microprocessor is further configured to perform power management on the optoelectronic submodule through the power chip based on digital monitoring data of the optoelectronic submodule.
wherein the slave microprocessor is further configured to output a control current matching the control signal to the light source unit in a current-type digital-to-analog conversion manner or output a control voltage matching the control signal to the light source unit in a voltage-type digital-to-analog conversion manner.
See note below
Claim 2: The co-packaged integrated optoelectronic module according to claim 1, further comprising: a light source unit connected to the optical transceiver chip and the slave microprocessor and configured to output another optical analog signal to the optical transceiver chip for transmission based on a control signal from the slave microprocessor.
Claim 5. wherein the slave microprocessor is further configured to output a control current matching the control signal to the light source unit in a current-type digital-to-analog conversion manner or output a control voltage matching the control signal to the light source unit in a voltage-type digital-to-analog conversion manner.
It has been held that the omission of an element and its function is obvious
expedient if the remaining elements perform the same function as before.
In re Karlson, 136 USPQ 184 (CCPA). Also note Ex parte Rainu, 168 USPQ 375 (bd.
App. 1969); the omission of a reference element whose function is not needed would be
obvious to one of ordinary skill in the art. Therefore, the omission of power chip and its function is an obvious expedient if the remaining elements perform the same function as before.
Claim 2 of 18/896335
Claim 3 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit comprises one or an even number of lasers, and the light source unit is configured to output another optical analog signal having a single wavelength through the one or the even number of lasers.
The co-packaged integrated optoelectronic module according to claim 2, wherein the light source unit comprises one or an even number of lasers, and the light source unit is configured to output another optical analog signal having a single wavelength through the one or the even number of lasers.
Claim 3 of 18/896335
Claim 4 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit comprises an even number of lasers, and the light source unit is configured to output another optical analog signal having different wavelengths through the even number of lasers.
The co-packaged integrated optoelectronic module according to claim 2, wherein the light source unit comprises an even number of lasers, and the light source unit is configured to output another optical analog signal having different wavelengths through the even number of lasers.
Claim 4 of 18/896335
Claim 6 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit.
The co-packaged integrated optoelectronic module according to claim 2, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit.
Claim 5 of 18/896335
Claim 7 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit is integrated into the optoelectronic submodule.
The co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit is integrated into the optoelectronic submodule.
Claim 6 of 18/896335
Claim 8 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, wherein the slave microprocessor is integrated into the optoelectronic submodule.
The co-packaged integrated optoelectronic module according to claim 1, wherein the slave microprocessor is integrated into the optoelectronic submodule.
Claim 7 of 18/896335
Claim 9 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, wherein the number of the optoelectronic submodule is one or an even number.
The co-packaged integrated optoelectronic module according to claim 1, wherein the number of the optoelectronic submodule is one or an even number.
Claim 8 of 18/896335
Claim 1 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, further comprising a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor.
a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor; wherein the slave microprocessor is further configured to perform power management on the optoelectronic submodule through the power chip based on digital monitoring data of the optoelectronic submodule.
Claim 9 of 18/896335
Claim 1 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 8, wherein the slave microprocessor is further configured to perform power management on the optoelectronic submodule through the power chip based on digital monitoring data of the optoelectronic submodule.
a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor; wherein the slave microprocessor is further configured to perform power management on the optoelectronic submodule through the power chip based on digital monitoring data of the optoelectronic submodule.
Claim 10 of 18/896335
Claim 10 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, further comprising a non-volatile memory connected to the master microprocessor and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module.
The co-packaged integrated optoelectronic module according to claim 1, further comprising a non-volatile memory connected to the master microprocessor and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module.
Claim 11 of 18/896335
Claim 11 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 1, further comprising a connection port disposed on and electrically connected to the carrier board and configured to electrically connect to an external circuit.
The co-packaged integrated optoelectronic module according to claim 1, further comprising a connection port disposed on and electrically connected to the carrier board and configured to electrically connect to an external circuit.
Claim 12 of 18/896335
Claim 12 of U.S. Patent No. 12136952
The co-packaged integrated optoelectronic module according to claim 11, wherein the connection port is a ball grid array (BGA) socket connector, a land grid array (LGA) socket connector or a golden finger interface.
The co-packaged integrated optoelectronic module according to claim 11, wherein the connection port is a ball grid array (BGA) socket connector, a land grid array (LGA) socket connector or a golden finger interface.
Claim 13 of 18/896335
Claim 13 of U.S. Patent No. 12136952
A co-packaged optoelectronic switch chip, comprising:
A co-packaged optoelectronic switch chip, comprising:
a switch application specific integrated circuit (ASIC);
a switch application specific integrated circuit (ASIC);
an even number of the co-packaged integrated optoelectronic modules according to claim 1, which are respectively electrically connected to the switch ASIC; and
an even number of the co-packaged integrated optoelectronic modules according to claim 1, which are respectively electrically connected to the switch ASIC; and
a substrate, wherein the even number of the co-packaged integrated optoelectronic modules and the switch ASIC are disposed on and electrically connected to the substrate, and the even number of the co-packaged integrated optoelectronic modules surround the switch ASIC.
a substrate, wherein the even number of the co-packaged integrated optoelectronic modules and the switch ASIC are disposed on and electrically connected to the substrate, and the even number of the co-packaged integrated optoelectronic modules surround the switch ASIC.
Claim 14 of 18/896335
Claim 14 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a connection port, and the co-packaged integrated optoelectronic module is electrically connected to the substrate through the connection port to electrically connect to the switch ASIC.
The co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a connection port, and the co-packaged integrated optoelectronic module is electrically connected to the substrate through the connection port to electrically connect to the switch ASIC.
Claim 15 of 18/896335
Claim 15 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 14, wherein the connection port is a BGA socket connector, a LGA socket connector or a golden finger interface.
The co-packaged optoelectronic switch chip according to claim 14, wherein the connection port is a BGA socket connector, a LGA socket connector or a golden finger interface.
Claim 16 of 18/896335
Claim 17 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor.
The co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor.
Claim 17 of 18/896335
Claim 18 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 13, wherein the co- packaged integrated optoelectronic module further comprises a non-volatile memory connected to the master microprocessor and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module.
The co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a non-volatile memory connected to the master microprocessor and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module.
Claim 18 of 18/896335
Claim 6 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 13, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit.
The co-packaged integrated optoelectronic module according to claim 2, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit.
Claim 19 of 18/896335
Claim 3 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 13, wherein the light source unit comprises one or an even number of lasers, and the light source unit is configured to output another optical analog signal having a single wavelength through the one or the even number of lasers.
The co-packaged integrated optoelectronic module according to claim 2, wherein the light source unit comprises one or an even number of lasers, and the light source unit is configured to output another optical analog signal having a single wavelength through the one or the even number of lasers.
Claim 20 of 18/896335
Claim 7 of U.S. Patent No. 12136952
The co-packaged optoelectronic switch chip according to claim 13, wherein the light source unit is integrated into the optoelectronic submodule.
The co-packaged integrated optoelectronic module according to claim 2, wherein the light source unit is integrated into the optoelectronic submodule.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
For claim 1,
a. a light source unit configured to output… on line 23.
For claim 2,
a. a light source unit is configured to output… on line 2,3.
For claim 3,
a. a light source unit is configured to output… on lines 2,3.
For claim 19,
a. a light source unit is configured to output… on line 23.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
a. the light source unit 15 may include one or an even number of lasers 151, see
paragraph 40 and figure 5.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1,2,3,4,5,6,7,8,9,10,13,16 and 17 are rejected under 35 USC 103 as being unpatentable over Yamaguchi et al; (WO 2021/171438) in view of Robert et al; (EP 3121630 A1) and further in view of Bovington et al; (US 2022/0037855).
Regarding claim 1, Yamaguchi discloses a co-packaged integrated optoelectronic module ;(opto-electronic fusion switch 100 with processor 20 and optical transceiver 30 integrated on substrate 11; see figures 2a, 2b) comprising: an optoelectronic submodule,(opto-electronic module ; see figure 2b) comprising: a digital signal processing chip ;(network processor 20; see figure 2a) configured to convert an electrical analog signal, which is received, into an electrical digital signal, and process the electrical digital signal to output a high-speed digital signal;( the network processor 20 is an electronic circuit that controls the function of the packet switch, and can input and output a large number of high-speed signals; see description of Embodiments and paragraph 3 and figure 2a) an optoelectronic signal chip connected to the digital signal processing chip and configured to convert an optical analog signal into the electrical analog signal to the digital signal processing chip;(each optical transmitter / receiver 30 is provided in the vicinity of the network processor 20 and each optical transmitter / receiver 30A converts the input optical signal into an electric signal and transmits it to the network processor 20A, and outputs an optical signal related to the electric signal from the network processor 20A; see embodiment 1 and paragraph 4 and figure 3) and an optical transceiver chip connected to the optoelectronic and configured to receive and transmit the optical analog signal to the optoelectronic signal chip, and transmit another optical signal;( each optical transmitter / receiver 30A outputs an optical signal obtained by electro-optically converting an electric signal from the network processor 20A to each output port Pout via each optical output path selection switch 72; see embodiment 1 and paragraph 4 and figure 3), a carrier board;( the metal wiring 40, and the optical waveguide 50 in the optical electron fusion switch 100 are mounted on the upper surface of the same substrate 11; see figure 2b) wherein the optoelectronic submodule, the slave microprocessor and the master microprocessor are disposed on and electrically connected to the carrier board ;(the network processor 20, each optical transceiver 30, each optical switch 20 the metal wiring 40, and the optical waveguide 50 in the optical electron fusion switch 100 are mounted on the upper surface of the same substrate 11; see figure 2b).
However Yamaguchi does not explicitly disclose a slave microprocessor connected to the optoelectronic submodule and configured to monitor operation of the optoelectronic submodule; a master microprocessor connected to the optoelectronic submodule and configured to process a low-speed digital signal transmitted from the co-packaged integrated optoelectronic module to the outside, monitor operation of the co- packaged integrated optoelectronic module, and perform initialization of the co- packaged integrated optoelectronic module; and signal analog conversion chip; analog signal, a light source unit connected to the optical transceiver chip and the slave microprocessor and configured to output the another optical analog signal to the optical transceiver chip for transmission based on a control signal from the slave microprocessor; wherein the slave microprocessor is further configured to output a control current matching the control signal to the light source unit in a current-type digital-to-analog conversion manner, or output a control voltage matching the control signal to the light source unit in a voltage-type digital-to-analog conversion manner.
In a related field of endeavor, Robert discloses a slave microprocessor ;(VCSEL driver; see figure 3) connected to the optoelectronic submodule and configured to monitor operation of the optoelectronic submodule; (the VCSEL is driven by a belonging driver under the control of a microcontroller in order to convert electric signals into optical signals; see paragraph 34 and figure 3) a master microprocessor (microcontroller; see figure 3) connected to the optoelectronic submodule (microcontroller coupled with the optical transceiver chip; see figure 3).
and perform initialization of the co- packaged integrated optoelectronic module;(microcontroller providing initialization (INT) function to the optical transceiver chip; see figure 3), a light source unit ;(vertical cavity surface emitting laser (VCSEL); see figure 3) connected to the optical transceiver chip and the slave microprocessor and configured to output another optical to the optical transceiver chip for transmission based on a control signal from the slave microprocessor; (the VCSEL is driven by a belonging driver under the control of a microcontroller in order to convert electric signals into optical signals; see paragraph 34 and figure 3).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the laser driver and microcontroller of Roberts with Yamaguchi to provide initialization function the optical transceiver chip and the motivation is to provide biasing current to the optoelectronic module.
However, the combination of Yamaguchi and Roberts does not explicitly disclose configured to process a low-speed digital signal transmitted from the co-packaged integrated optoelectronic module to the outside, monitor operation of the co- packaged integrated optoelectronic module and signal analog conversion chip; analog signal, wherein the slave microprocessor is further configured to output a control current matching the control signal to the light source unit in a current-type digital-to-analog conversion manner, or output a control voltage matching the control signal to the light source unit in a voltage-type digital-to-analog conversion manner.
In a related field of endeavor, Bovington discloses configured to process a low-speed digital signal transmitted from the co-packaged integrated optoelectronic module to the outside, monitor operation of the co- packaged integrated optoelectronic module (the logic controller 450, receives electrical signals from the photodiode 445 that are representative of the average optical power, and outputs electrical signals to the laser driver 405 to control the bias/driving voltage of the laser diode 405; see paragraph 35 and figure 4A) and signal analog conversion chip; analog signal; (the logic controller 450 includes the analog-to-digital converter, see paragraph 33), wherein the slave microprocessor is further configured to output a control current matching the control signal to the light source unit in a current-type digital-to-analog conversion manner, or output a control voltage matching the control signal to the light source unit in a voltage-type digital-to-analog conversion manner (the logic controller 450, receives electrical signals from the photodiode 445 that are representative of the average optical power, and outputs electrical (current/voltage) signals to the laser driver 405 to control the bias/driving voltage of the laser diode 405 and wherein the logic controller 450 includes the analog-to-digital converter, see paragraph 33 see paragraph 35 and figure 4A).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the monitoring of the optical transceiver module of Bovington with Yamaguchi and Roberts to measure the output power at the output and the motivation is to provide generate required bias voltage for a laser generation the carrier wave and high speed digital signal.
Regarding claim 2, Yamaguchi does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit comprises one or an even number of lasers, and the light source unit is configured to output another optical analog signal having a single wavelength through the one or the even number of lasers.
In a related field of endeavor, Roberts discloses the co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit comprises one or an even number of lasers ;(four vertical cavity surface emitting laser (VCSEL); Ch0, Ch1, Ch2 and Ch3; see figure 3) and the light source unit is configured to output another optical signal having a single wavelength through the one or the even number of lasers; (four vertical cavity surface emitting laser (VCSEL); Ch0, Ch1, Ch2 and Ch3 for emitting different wavelength channels; see figure 3). Motivation same as claim 1.
However, the combination of Yamaguchi and Roberts does not explicitly disclose analog signal.
In a related field of endeavor, Bovington discloses analog signal (the logic controller 450 includes the analog-to-digital converter, see paragraph 33). Motivation same as claim 1.
Regarding claim 3, Yamaguchi does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit comprises an even number of lasers, and the light source unit is configured to output another optical analog signal having different wavelengths through the even number of lasers.
In a related field of endeavor, Roberts discloses the co-packaged integrated optoelectronic module according to claim 2, wherein the light source unit comprises an even number of lasers;(four vertical cavity surface emitting laser (VCSEL); Ch0, Ch1, Ch2 and Ch3; see figure 3) and the light source unit is configured to output another optical signal having different wavelengths through the even number of lasers (four vertical cavity surface emitting laser (VCSEL); Ch0, Ch1, Ch2 and Ch3 for emitting different wavelength channels; see figure 3). Motivation same as claim 1.
However, the combination of Yamaguchi and Roberts does not explicitly disclose analog signal.
In a related field of endeavor, Bovington discloses analog signal (the logic controller 450 includes the analog-to-digital converter, see paragraph 33). Motivation same as claim 1.
Regarding claim 4, the combination of Yamaguchi and Roberts does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 1, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit.
In a related field of endeavor, Bovington discloses the co-packaged integrated optoelectronic module according to claim 2, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit; (the logic controller 450, receives electrical signals from the photodiode 445 that are representative of the average optical power (monitoring data), and outputs electrical (current/voltage) signals to the laser driver 405 to control the bias/driving voltage of the laser diode 405; see paragraph 35 and figure 4A). Motivation same as claim 1.
Regarding claim 5, Yamaguchi discloses the co-packaged integrated optoelectronic module according to claim 1, wherein the light source unit is integrated into the optoelectronic submodule ;(each optical transmitter / receiver 30 is provided in the vicinity of the network processor 20 and substrate 11; see figure 2b).
Regarding claim 6, Yamaguchi discloses the co-packaged integrated optoelectronic module according to claim 1, wherein the slave microprocessor is integrated into the optoelectronic submodule ;(the network processor 20 of optical electron fusion switch 100 are mounted on the upper surface of the substrate 11; see figure 2b).
Regarding claim 7, Yamaguchi discloses the co-packaged integrated optoelectronic module according to claim 1, wherein the number of the optoelectronic submodule is one ;(each optical transmitter / receiver 30 is provided in the vicinity of the network processor 20 and substrate 11; see figure 2b) or an even number. Only one of the claim limitation is required to be considered by the Examiner.
Regarding claim 8, the combination of Yamaguchi and Roberts does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 1, further comprising a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor.
In a related field of endeavor, Bovington discloses the co-packaged integrated optoelectronic module according to claim 1, further comprising a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor; ( the photodiode 445 measures Average optical power (AOP) of the modulated optical wave to report the optical power of the modulated optical wave to the logic controller 450 as an electrical signal and the adjustment of bias is based on the AOP reading when AOP reading is above a threshold value to conserve power or maintain a constant output power for the optical signal; see paragraph 41 and 44 and figures 4a, 5). Motivation same as claim 1.
Regarding claim 9, the combination of Yamaguchi and Roberts does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 8, wherein the slave microprocessor is further configured to perform power management on the optoelectronic submodule through the power chip based on digital monitoring data of the optoelectronic submodule.
In a related field of endeavor, Bovington discloses the co-packaged integrated optoelectronic module according to claim 8, wherein the slave microprocessor is further configured to perform power management on the optoelectronic submodule through the power chip based on digital monitoring data of the optoelectronic submodule; ( the photodiode 445 measures Average optical power (AOP) of the modulated optical wave to report the optical power of the modulated optical wave to the logic controller 450 as an electrical signal and the adjustment of bias is based on the AOP reading when AOP reading is above a threshold value to conserve power or maintain a constant output power for the optical signal; see paragraph 41 and 44 and figures 4a, 5). Motivation same as claim 1.
Regarding claim 10, the combination of Yamaguchi and Bovington does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 1, further comprising a non-volatile memory connected to the master microprocessor and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module.
In a related field of endeavor, Roberts discloses the co-packaged integrated optoelectronic module according to claim 1, further comprising a non-volatile memory ;(memory map in the microcontroller; see figure 3) connected to the master microprocessor (microcontroller; see figure 3) and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module;(microcontroller providing initialization (INT) function to the optical transceiver chip; see figure 3).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the microcontroller of Roberts with Yamaguchi and Bovington to provide initialization function the optical transceiver chip and the motivation is to provide biasing current to the optoelectronic module.
Regarding claim 13, Yamaguchi discloses a co-packaged optoelectronic switch chip ;(opto-electronic fusion switch 100 with processor 20 and optical transceiver 30 integrated on substrate 11; see figures 2a, 2b) comprising: a switch application specific integrated circuit (ASIC); (processor 20 see figure 2a)an even number of the co-packaged integrated optoelectronic modules according to claim 1, which are respectively electrically connected to the switch ASIC;(eight optical transmitters /receivers (30A) having a photoelectric conversion function coupled with the network processor 20; see figure 2a) and a substrate;(substrate 11; see figure 2b) wherein the even number of the co-packaged integrated optoelectronic modules and the switch ASIC are disposed on and electrically connected to the substrate, and the even number of the co-packaged integrated optoelectronic modules surround the switch ASIC ;(the network processor 20, each optical transceiver 30, each optical switch 20 the metal wiring 40, and the optical waveguide 50 in the optical electron fusion switch 100 are mounted on the upper surface of the same substrate 11; see figure 2b).
Regarding claim 16, the combination of Yamaguchi and Roberts does not explicitly disclose the co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor.
In a related field of endeavor, Bovington discloses the co-packaged optoelectronic switch chip according to claim 13, wherein the co- packaged integrated optoelectronic module further comprises a power chip configured to provide power to the optoelectronic submodule, the slave microprocessor and the master microprocessor; ( the photodiode 445 measures Average optical power (AOP) of the modulated optical wave to report the optical power of the modulated optical wave to the logic controller 450 as an electrical signal and the adjustment of bias is based on the AOP reading when AOP reading is above a threshold value to conserve power or maintain a constant output power for the optical signal; see paragraph 41 and 44 and figures 4a, 5). Motivation same as claim 1.
Regarding claim 17, the combination of Yamaguchi and Bovington does not explicitly disclose the co-packaged optoelectronic switch chip according to claim 13, wherein the co- packaged integrated optoelectronic module further comprises a non-volatile memory connected to the master microprocessor and configured to store an initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module.
In a related of endeavor, Roberts discloses the co-packaged optoelectronic switch chip according to claim 15, wherein the co- packaged integrated optoelectronic module further comprises a non-volatile memory;(memory map in the microcontroller; see figure 3) connected to the master microprocessor (microcontroller; see figure 3) and configured to store a initialization program required by the master microprocessor to perform initialization of the co-packaged integrated optoelectronic module ;(microcontroller providing initialization (INT) function to the optical transceiver chip; see figure 3).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the microcontroller of Roberts with Yamaguchi to provide initialization function the optical transceiver chip and the motivation is to provide biasing current to the optoelectronic module.
Claims 11,12,14,15,18,19 and 20 are rejected under 35 USC 103 as being unpatentable over Yamaguchi et al; (WO 2021/171438) in view of Robert et al; (EP 3121630 A1), further in view of Bovington et al; (US 2022/0037855) and further in view of Lu et al; (US 7373033).
Regarding claim 11, the combination of Yamaguchi, Robert and Bovington does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 1, further comprising a connection port disposed on and electrically connected to the carrier board and configured to electrically connect to an external circuit.
In a related field of endeavor, Luo discloses the co-packaged integrated optoelectronic module according to claim 1, further comprising a connection port disposed on and electrically connected to the carrier board and configured to electrically connect to an external circuit; (the electrical terminal array on chip side 145 of substrate 120 is electrically coupled to electrical terminal array 155 on landside 140 of substrate 120 through electrical vias 160. When substrate 120 is mated to socket 105, electrical terminal array 155 couples to corresponding electrical terminal array 130, which then forms connections through socket 105 to external chips mounted on the same circuit board as socket 105; see column 3; lines 12-20; see figures 1a, 1b and 1c).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the electrical socket of Luo with Yamaguchi, Robert and Bovington to provide electrical connection between different components on the substrate and the motivation is to provide power to different components on the substrate.
Regarding claim 12, the combination of Yamaguchi, Robert and Bovington does not explicitly disclose the co-packaged integrated optoelectronic module according to claim 13, wherein the connection port is a ball grid array (BGA) socket connector, a land grid array (LGA) socket connector or a golden finger interface.
In a related field of endeavor, Luo discloses the co-packaged integrated optoelectronic module according to claim 13, wherein the connection port is a ball grid array (BGA) socket connector, a land grid array (LGA) socket connector ;( substrate 120 is mated to socket 105, electrical terminal array 155 couples to corresponding electrical terminal array 130, which then forms connections through socket 105 to external chips mounted on the same circuit board as socket 105. In one embodiment, electrical terminal array 155 is a land grid array ("LGA"); see column 3, lines 15-22 and figures 1a, 1b and 1c) or a golden finger interface. (Only one of the claim limitation is required to be considered by the Examiner).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the LGA socket of Luo with Yamaguchi, Robert and Bovington to provide electrical connection between different components on the substrate and the motivation is to provide power to different components on the substrate.
Regarding claim 14, the combination of Yamaguchi, Robert and Bovington does not explicitly disclose the co-packaged optoelectronic switch chip according to claim 13, wherein the co-packaged integrated optoelectronic module further comprises a connection port, and the co-packaged integrated optoelectronic module is electrically connected to the substrate through the connection port to electrically connect to the switch ASIC.
In a related field of endeavor, Luo discloses the co-packaged optoelectronic switch chip according to claim 13, wherein the co- packaged integrated optoelectronic module further comprises a connection port, and the co-packaged integrated optoelectronic module is electrically connected to the substrate through the connection port to electrically connect to the switch ASIC; (the electrical terminal array on chip side 145 of substrate 120 is electrically coupled to electrical terminal array 155 on landside 140 of substrate 120 through electrical vias 160. When substrate 120 is mated to socket 105, electrical terminal array 155 couples to corresponding electrical terminal array 130, which then forms connections through socket 105 to external chips mounted on the same circuit board as socket 105; see column 3; lines 12-20; see figures 1a, 1b and 1c).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the electrical socket of Luo with Yamaguchi, Robert and Bovington to provide electrical connection between different components on the substrate and the motivation is to provide power to different components on the substrate.
Regarding claim 15, the combination of Yamaguchi, Robert and Bovington does not explicitly disclose the co-packaged optoelectronic switch chip according to claim 14, wherein the connection port is a BGA socket connector, a LGA socket connector or a golden finger interface.
In a related field of endeavor, Luo discloses the co-packaged optoelectronic switch chip according to claim 14, wherein the connection port is a BGA socket connector, a LGA socket connector ;( substrate 120 is mated to socket 105, electrical terminal array 155 couples to corresponding electrical terminal array 130, which then forms connections through socket 105 to external chips mounted on the same circuit board as socket 105. In one embodiment, electrical terminal array 155 is a land grid array ("LGA"); see column 3, lines 15-22 and figures 1a, 1b and 1c) or a golden finger interface. Only one of the claim limitation is required to be considered by the Examiner).
Thus, it would be obvious for one of the ordinary skilled in the art before the effective filling date of the invention to combine the LGA socket of Luo with Yamaguchi, Robert and Bovington to provide electrical connection between different components on the substrate and the motivation is to provide power to different components on the substrate.
Regarding claim 18, the combination of Yamaguchi, Roberts and Luo does not explicitly disclose the co-packaged optoelectronic switch chip according to claim 13, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit.
In a related field of endeavor, Bovington discloses the co-packaged optoelectronic switch chip according to claim 13, wherein the slave microprocessor is further configured to perform closed loop control of the optoelectronic submodule and the light source unit according to digital monitoring data of the optoelectronic submodule and the light source unit (the logic controller 450, receives electrical signals from the photodiode 445 that are representative of the average optical power (monitoring data), and outputs electrical (current/voltage) signals to the laser driver 405 to control the bias/driving voltage of the laser diode 405; see paragraph 35 and figure 4A). Motivation same as claim 1.
Regarding claim 19, the combination of Yamaguchi and Luo does not explicitly disclose the co-packaged optoelectronic switch chip according to claim 13, wherein the light source unit comprises one or an even number of lasers, and the light source unit is configured to output another optical analog signal having a single wavelength through the one or the even number of lasers.
In a related field of endeavor, Roberts discloses the co-packaged integrated optoelectronic switch chip according to claim 13, wherein the light source unit comprises an even number of lasers;(four vertical cavity surface emitting laser (VCSEL); Ch0, Ch1, Ch2 and Ch3; see figure 3) and the light source unit is configured to output another optical signal having different wavelengths through the even number of lasers (four vertical cavity surface emitting laser (VCSEL); Ch0, Ch1, Ch2 and Ch3 for emitting different wavelength channels; see figure 3). Motivation same as claim 1.
However, the combination of Yamaguchi, Roberts and Luo does not explicitly disclose analog signal.
In a related field of endeavor, Bovington discloses analog signal (the logic controller 450 includes the analog-to-digital converter, see paragraph 33). Motivation same as claim 1.
Regarding claim 20, Yamaguchi discloses the co-packaged optoelectronic switch chip according to claim 13, wherein the light source unit is integrated into the optoelectronic submodule ;(each optical transmitter / receiver 30 is provided in the vicinity of the network processor 20 and substrate 11; see figure 2b).
Conclusion
4. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is reproduced below.
a. Nagarajan et al; (US 2021/0385000) discloses four sub-assemblies of optical-electrical sub-modules with at least four laser chips, driver chip, TIA chip and electrical interface on sub-module substrate; see figure 2.
b. Dos Santos Fegadolli et al; (US 2021/0333494) discloses substrate with metallic connectors with one or more digital signal processing chips, optical fiber interfaces 16a, 16b and heat sinks 18 and 20; see figure 1.
c. Tian et al; (Experimental demonstration of a reconfigurable electro-optic directed logic circuit using cascaded carrier-injection micro-ring resonators – July 2018 attached) discloses a reconfigurable electro-optic directed logic circuit which can perform
any combinatorial logic operation using cascaded carrier-injection micro-ring resonators, and the logic circuit is fabricated on the silicon-on-insulator substrate; see figure 3
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/AMRITBIR K SANDHU/Primary Examiner, Art Unit 2634
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