DETAILED ACTION
This Office action is in response to the filing of this application on 26 September 2024. Claims 1-9 are pending in the application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-7 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Yamazaki et al., US 20150263141.
With respect to claim 1, Yamazaki et al. disclose a semiconductor device, shown in Fig. 7D, comprising:
an oxide semiconductor layer 54 (see Fig. 7A and paragraph [0223]) provided above an insulating surface 53 (see Fig. 7A and paragraph [0223]);
a gate insulating layer 56 (see Fig. 7A and paragraph [0223] provided above the oxide semiconductor layer 54; and
a gate electrode 58a/61 provided above the oxide semiconductor layer 54 via the gate insulating layer 56 (see Figs. 7A and 7D),
wherein the gate electrode 58a/61 has a titanium-containing layer 58a (see paragraph [0228]) and a conductive layer 61 (see paragraph [0230]) in order from the gate insulating layer 56 side (as shown in Fig. 7D),
the gate insulating layer 56 includes a first region overlapping the gate electrode 58a/61 and a second region not overlapping the gate electrode, as shown in Fig. 7D, and
a thickness of the titanium-containing layer 58a is 50% or less than a thickness of the gate insulating layer 56 in the first region. Yamazaki et al. disclose in paragraph [0165] that the titanium-containing layer 58a has a thickness greater than or equal to 1 nm and less than or equal to 20 nm. Yamazaki et al. disclose that the gate insulating layer 56 has a thickness of greater than or equal to 5 nm and less than or equal to 100 nm, see paragraph [0213]. Hence, based on the disclosure of Yamazaki et al., a thickness of the titanium-containing layer 58a is 50% or less than a thickness of the gate insulating layer 56 in the first region.
With respect to claim 3, in the device of Yamazaki et al., a thickness of the first region of the gate insulating layer is 100 nm or more and 125 nm or less, see paragraph [0213].
With respect to claim 4, in the semiconductor device of Yamazaki et al., the thickness of the titanium-containing layer 58a is 25% or more and less than 70% of the thickness of the gate insulating layer 56 in the second region. As shown in Fig. 7D, in the second region the thickness of titanium-containing layer 58a can be 12.5 nm (see paragraph [0165]), which is 25% of the thickness of the gate insulating layer 56 in the second region, which can be 50 nm (see paragraph [0213]).
With respect to claim 5, in the semiconductor device of Yamazaki et al., a thickness of the second region of the gate insulating layer is 75 nm or more and 100 nm or less, see paragraph [0213].
With respect to claim 6, the titanium-containing layer 58a is a titanium layer, see paragraph [0228]. The titanium-containing layer 58a is a titanium layer to which oxygen 62 is added.
With respect to claim 7, in the device of Yamazaki et al., the titanium-containing layer includes a titanium layer and a titanium nitride layer, since Yamazaki et al. discloses that the titanium-containing layer can comprise titanium and titanium oxynitride, see paragraph [0213].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al., US 20150263141, as applied to claim 1 above.
Yamazaki et al. discloses that the thickness of the titanium-containing layer 58a can be greater than or equal to 1 nm and less than or equal to 20 nm, see paragraph [0165]. In claim 2, Applicant requires the thickness of the titanium-containing layer to be 25 nm or more and 50 nm or less. Admittedly, Applicant’s claimed thickness is not taught by Yamazaki et al. However, Yamazaki et al. clearly disclose that a thickness of the titanium-containing layer 58a must be 50% or less than a thickness of the gate insulating layer 56 in the first region. It has been well established that where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) In light of the disclosure of Yamazaki et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the thickness of the titanium-containing layer could be 25 nm or more and 50 nm or less, as long as the thickness of the titanium-containing layer 58a is 50% or less than the thickness of the gate insulating layer 56 in the first region. It would have been obvious to the skilled artisan to optimize the thickness of the titanium-containing layer, and this thickness would be ascertainable through routine optimization within the prior art conditions disclosed by Yamazaki et al. The claimed thickness of the titanium-containing layer is not deemed to patentably distinguish Applicant’s claimed semiconductor device from the prior art device of Yamazaki et al.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable Yamazaki et al., US 20150263141, as applied to claim 1 above, in view of Oikawa et al., US 2021/0288183.
Yamazaki et al. is applied as above in the rejection of independent claim 1. Yamazaki et al. fail to disclose an aluminum-based metal oxide layer provided over the insulating surface 53 in contact with a bottom of the oxide semiconductor layer 54. In the same field of endeavor, Oikawa et al. disclose an oxide semiconductor layer 108 which includes an oxide semiconductor layer 108b and an oxide semiconductor layer 108c, as shown in Fig. 1B, wherein the oxide semiconductor layers 108b and 108c both contain In, M (M is Al, Ga, Y, or Sn), and Zn, see paragraphs [0085]-[0087]..This arrangement yields a transistor having mobility exceeding 30 cm.sup.2/Vs. In light of the disclosure of Oikawa et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that an aluminum-based metal oxide layer could be provided over the insulating surface 53 in contact with a bottom of the oxide semiconductor layer 54 in the known device of Yamazaki et al. to fabricate a thin film transistor having mobility exceeding 30 cm.sup.2/Vs.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable Yamazaki et al., US 20150263141, as applied to claim 1 above, in view of Lee et al., 2018/0374956.
Yamazaki et al. is applied as above. Although Yamazaki et al. disclose an oxide semiconductor layer 54, Yamazaki et al. fail to disclose the oxide semiconductor layer.54 contains two metallic elements including indium, and a ratio of indium in the oxide semiconductor layer could be 50% or more. In the same field of endeavor, Lee et al. disclose a thin film transistor exhibiting excellent mobility and reliability in which the oxide semiconductor layer 120 comprising gallium, indium, zinc, and tin comprises 50% indium, see paragraph [0073]-[0074]. Therefore, in light of the disclosure of Lee et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the oxide semiconductor layer 54 in the known device of Yamazaki et al. could contain two metallic elements including indium, and a ratio of indium in the oxide semiconductor layer could be 50%.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additionally cited references disclose various thin film transistor devices having multi-layered gate electrodes.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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