Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated June 9, 2026, claims 1-20 are active in
this application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 15 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the phrase "based on predetermined erase speed characteristics" is ambiguous. Because the specification allows for multiple ways to group word lines (during design or dynamically during the device's lifetime) and allows lines to shift zones as they age, it is hard to determine the actual boundaries of what a "zone" or group contains at any given moment.
Claims 2-8, 15 and 16 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claims 9-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 9, the phrase "based on predetermined erase speed characteristics" is ambiguous. Because the specification allows for multiple ways to group word lines (during design or dynamically during the device's lifetime) and allows lines to shift zones as they age, it is hard to determine the actual boundaries of what a "zone" or group contains at any given moment.
Claims 10-14 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 17, the phrase "based on predetermined erase speed characteristics" is ambiguous. Because the specification allows for multiple ways to group word lines (during design or dynamically during the device's lifetime) and allows lines to shift zones as they age, it is hard to determine the actual boundaries of what a "zone" or group contains at any given moment.
Claims 18-20 are rejected because they depend on the indefiniteness of the claims from which they depend.
Claim Rejections- 35 U.S.C. § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-5, 7, 8, 15 and 16 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Yang [US Patent # 7,630,255].
With respect claim 1, Yang discloses a method of performing an erase operation in a memory device ["A method for erasing data of a NAND flash memory device..." – col. 1, lines 60-67; and col. 2, lines 1-20 (The patent directly addresses the memory operation described.)], comprising the steps of: preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines ["...each block including a plurality of cell strings, each string including drain and source selection transistors and a plurality of memory cells, may include applying a first erase voltage to memory cells of a block to be erased; performing a first verification to verify erased states of the memory cells of the block using a first verify voltage higher than a second verify voltage " - col. 1, lines 60-67; and col. 2, lines 1-20 (The structure involves standard NAND blocks with multiple cells/rows.)], the word lines being grouped into a plurality of zones [“classifying memory cells that have not passed the second verification process as a third group; and erasing data of the memory cells of the first, second, and third groups using different step voltages and different erase voltages.” – col. 2, lines 1-20 (The patent explicitly groups word lines/cells into different groups for separate erasing. It is noted that the patent shows a is a multi-step, multi-group erase operation. Because memory cells are connected to word lines in a block, separating them into first, second, and third groups to receive different erase voltages (e.g., 19V, 18V, 18.5V) means the word lines controlling those groups are implicitly treated as separate zones or groups within the block.) based on predetermined erase speed characteristics [The patent mentions using different step voltages for different groups, implying different erase characteristics. – see col. 2], and at least some of the memory cells being in programmed data states [Implicit in "erasing data". Memory must be programmed before it can be erased.]; erasing the memory cells of the word lines of a first zone of the plurality of zones using a first type of erase operation ["an erase operation is performed on the memory cells of the first group with the first erase voltage..." – col. 2 (the patent using a specific (first) type of erase for a specific (first) zone.)]; and erasing the memory cells of the word lines of a second zone of the plurality of zones using a second type of erase operation that is different than the first type of erase operation ["...second group with the second erase voltage increased in steps... different from the first" – col. 2 (the patent using a different (second) type of erase for a different (second) zone.)]. It is noted that Yang indicated that instead of a single erase voltage for all cells (which would be slow for "slow" cells and damaging for "fast" cells), the invention identifies groups that erase faster or slower. To achieve this, a "first type" of erase (e.g., 19V) is applied to a "first group" (slow) and a "second type" of erase (e.g., 18V) is applied to a "second group" (fast).
With respect to claim 3, Yang discloses the word lines of the first zone have slower erase speed characteristics than the word lines of the second zone. [“…this data erasure method may reduce the total erasure time since it selectively applies different erase voltages and different step voltages according to the erasure speeds of cells of blocks…” – col. 2, lines 45-55].
With respect to claim 4, Yang discloses the first type of erase operation includes a first word line voltage and the second type of erase operation includes a second word line voltage that is different than the first word line voltage [“ If the data stored in the flag bits is "01", the erase voltage is increased and applied in steps or a step voltage until a threshold is reached. For example, the step voltage may be a step of 1V until the erase voltage reaches a threshold of 18V (operations 200 to 206) (see FIG. 4A). Of course a different step voltage and a different threshold voltage may be used depending on the application. (16) If the data stored in the flag bits is "10", the erase voltage is increased and applied in steps until a threshold is reached. For example, the erase voltage may be increase in by a step voltage of 0.5V until the erase voltage reaches a threshold of 18.5V (operations 300 to 306) (see FIG. 4B). Of course a different step voltage and a different threshold voltage may be used based upon the application.” – col. 4, lines 15-30].
With respect to claim 5, Yang discloses the word lines of the first zone have slower erase speed characteristics than the word lines of the second zone. [“…this data erasure method may reduce the total erasure time since it selectively applies different erase voltages and different step voltages according to the erasure speeds of cells of blocks…” – col. 2, lines 45-55].
With respect to claim 7, Yang discloses the plurality of zones further includes at least three zones [“…classifying memory cells that have not passed the second verification process as a third group; and erasing data of the memory cells of the first, second, and third groups using different step voltages and different erase voltages.” – col. 2, lines 10-15].
With respect to claim 8, Yang discloses at least one of the zones includes word lines that are not adjacent to the other word lines of the same zone [...and erasing data of the memory cells of the first, second, and third groups using different step voltages and different erase voltages." – col. 2, lines 1-30 ( This confirms that the groups (slow, fast, medium) are treated differently to ensure efficient erasing without over-erasing cells, based on their speed characteristics.)]
With respect to claim 15, Yang discloses the plurality of zones further includes at least three zones [“…classifying memory cells that have not passed the second verification process as a third group; and erasing data of the memory cells of the first, second, and third groups using different step voltages and different erase voltages.” – col. 2, lines 10-15].
With respect to claim 16, Yang discloses at least one of the zones includes word lines that are not adjacent to the other word lines of the same zone [...and erasing data of the memory cells of the first, second, and third groups using different step voltages and different erase voltages." – col. 2, lines 1-30 ( This confirms that the groups (slow, fast, medium) are treated differently to ensure efficient erasing without over-erasing cells, based on their speed characteristics.)]
Claim(s) 9 and 11-13 is/are rejected, as understood, under 35 U.S.C. 102(a)(1) as being anticipated by Yang [US Patent # 7,630,255].
With respect claim 9, Yang discloses a memory device, comprising: a memory block that includes an array of memory cells that are arranged in a plurality of word lines [Yang indicates "NAND flash memory device including memory cell blocks" and states "each block including a plurality of cell strings, each string including drain and source selection transistors and a plurality of memory cells," with word lines (WL) controlling them – col. 2, lines 1-30 ], the word lines being grouped into a plurality of zones based on predetermined erase speed characteristics [primarily classifies cells based on "verify voltages" (failed to pass a higher vs lower voltage), this classification serves to differentiate them based on their physical response to the erase voltage (i.e., their erase speed/resistance). Cells that pass a low-voltage verification erase faster than those requiring a high-voltage verification. The patent explicitly separates the memory cells into "first, second, and third groups" (zones) based on their threshold voltage state after a partial erase – col. 2 (it is noted that the patent shows a process that is a multi-step, multi-group erase operation. Because memory cells are connected to word lines in a block, separating them into first, second, and third groups to receive different erase voltages (e.g., 19V, 18V, 18.5V) means the word lines controlling those groups are implicitly treated as separate zones or groups within the block.)], and at least some of the memory cells being in programmed data states [ The method is described for "erasing data of the memory cells" that are in a "programmed data state" – col. 2, last paragraph]; and circuitry for erasing the memory cells of the memory block, the circuitry being configured to; erase the memory cells of the word lines of a first zone of the plurality of zones using a first type of erase operation; and erase the memory cells of the word lines of a second zone of the plurality of zones using a second type of erase operation that is different than the first type of erase operation [ The patent details that after identifying groups, the circuitry is configured to perform an erase operation using "different step voltages and different erase voltages" for each group (col. 2). Specifically, a "first group" (fast-erasing) is treated differently than a "second group" (slow-erasing) to avoid over-erasure (cols. 2-4).]. It is noted that Yang indicated that instead of a single erase voltage for all cells (which would be slow for "slow" cells and damaging for "fast" cells), the invention identifies groups that erase faster or slower. To achieve this, a "first type" of erase (e.g., 19V) is applied to a "first group" (slow) and a "second type" of erase (e.g., 18V) is applied to a "second group" (fast).
With respect to claim 11, Yang discloses the word lines of the first zone have slower erase speed characteristics than the word lines of the second zone. [“…this data erasure method may reduce the total erasure time since it selectively applies different erase voltages and different step voltages according to the erasure speeds of cells of blocks…” – col. 2, lines 45-55].
With respect to claim 12, it is rejected as understood, Yang disclose the first type of erase operation includes a first word line voltage and the second type erase operation includes a second word line voltage that is different than the first erase voltage shift [“ If the data stored in the flag bits is "01", the erase voltage is increased and applied in steps or a step voltage until a threshold is reached. For example, the step voltage may be a step of 1V until the erase voltage reaches a threshold of 18V (operations 200 to 206) (see FIG. 4A). Of course a different step voltage and a different threshold voltage may be used depending on the application. (16) If the data stored in the flag bits is "10", the erase voltage is increased and applied in steps until a threshold is reached. For example, the erase voltage may be increase in by a step voltage of 0.5V until the erase voltage reaches a threshold of 18.5V (operations 300 to 306) (see FIG. 4B). Of course a different step voltage and a different threshold voltage may be used based upon the application.” – col. 4, lines 15-30].
With respect to claim 13, Yang discloses the word lines of the first zone have slower erase speed characteristics than the word lines of the second zone. [“…this data erasure method may reduce the total erasure time since it selectively applies different erase voltages and different step voltages according to the erasure speeds of cells of blocks…” – col. 2, lines 45-55].
Remarks
Applicant's arguments filed June 9, 2026 have been fully considered but they are not
persuasive.
Applicant argued that the “Yang’s groups are post-verify groups of memory cells, i.e., after the erase operation has already begun. Yang does not disclose word lines being grouped into zones based on predetermined erase speed characteristics before the claimed zone-specific erase operations.” The Examiner respectfully disagrees.
The examiner refers to the phrase “testing of natural erase depth using the same type of erase operation.” See par. 0113 of Applicant’s disclosure. Erase operations in memory devices inherently involve verifying whether the cells have been erased to an intended target level (Erase Verify). Therefore, an erase verify process functionally matches the testing of "natural erase depth." Additionally, because the specification notes that word lines can be assigned or re-assigned based on testing, and erase verify is a standard form of this testing, the prior art meets the structural limitations as described. Further, the specification clearly defines regrouping during the "operating life of the memory device" as an alternative embodiment. Because the specification explicitly describes reassigning a word line to a different zone if its speed characteristics change during operation, an argument restricting the groupings solely to the pre-operating phase fails to account for the full scope of the disclosure. Furthermore, the applied art uses an erase operation on all word lines to determine their grouping or speed, those word lines inherently have predetermined erase speed characteristics before they are actively sorted or re-grouped.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for response to this final action is set to expire THREE MONTHS from the date of this action. In the event a first response is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event will the statutory period for response expire later than SIX MONTHS from the date of this final action.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 July 21, 2026
Prosecution Insights