DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 11-15 and 20 objected to because of the following informalities:
Regarding claim 11: Change “the same group” to “a same group” and “the same verify voltage” to “a same verify voltage”.
Claims 12-15 depend on claim 11.
Regarding claim 20: The claim needs to be corrected in regards to grammar. It seems that a memory system is claimed that comprises a peripheral circuit that is configured to perform a set of method steps but then appended to this by “and” was further detail that the memory is also configured to perform the same set of method steps that the peripheral circuit was already claimed to be configured to do. Hence, the claims starting from “the memory configured to:” to the end seems to be redundant subject matter.
One way to fix this would be amend the claim as follows:
A memory system, comprising:
a controller; and
a memory coupled with the controller and comprising:
a memory cell array comprising memory cells of a target group;
a plurality of word lines coupled to rows of the memory cell array respectively;
a plurality of bit lines coupled to memory strings of the memory cell array respectively; and
a peripheral circuit coupled to the memory cell array through the word lines and the bit lines, and configured to: at a first program stage,
perform a program operation on the memory cells of the target group for a first number of times, wherein the memory cells of the target group comprise a first memory cell and a second memory cell, wherein a target program state of the first memory cell is a first program state, and a target program state of the second memory cell is a second program state;
perform a verify operation on the memory cells of the target group using a verify voltage for the target group; and
after the second memory cell passes the verification that uses the verify voltage for the target group, perform the program operation on the second memory cell for a second number of times, and inhibit the second memory cell from being verified
.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 10: This claim refers to “a second number of times” but “a second of times” was already introduced in claim 1 so it is indefinite as to whether the number is the same.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 and 6-7, 17, and 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cernea (2009/0310421).
Regarding claim 1: Cernea (FIG. 17, and FIG. 18a-b; [0153-0161) teaches a method for operating a memory, comprising: at a first program stage,
performing a program operation on memory cells of a target group for a first number of times (see 1.1 of FIG. 17, wherein a plurality of program pulses are illustrated and “x program pulses + verifying steps” in FIG. 18B), wherein the memory cells of the target group comprise a first memory cell and a second memory cell, a target program state of the first memory cell is a first program state (state “0” state in FIG. 18B), and a target program state of the second memory cell is a second program state (state “1” state in FIG. 18B);
performing a verify operation on the memory cells of the target group using a verify voltage for the target group (see section 1.1 in FIG. 17, wherein verify loops or pules are provided); and
after the second memory cell passes the verification that uses the verify voltage for the target group, performing the program operation on the second memory cell for a second number of times (one time/pulse see section 1.2 in FIG. 17 and FIG. 18B), and inhibiting the second memory cell from being verified (no verify loops are executed in 1.2 of FIG. 17; see “without having to verify” in [0155]).
Regarding claim 2: Cernea teaches the method of claim 1, wherein a threshold voltage of a memory cell in the first program state (state “0” state in FIG. 18B) is less than a threshold voltage of the memory cell in the second program state (state “1” state in FIG. 18B), the verify voltage for the target group is for verifying whether the memory cell is in a target intermediate state (state “0” state in FIG. 18B), wherein the target intermediate state is a program target for the first memory cell at the first program stage.
Regarding claim 3: Cernea teaches the method of claim 1, wherein a threshold voltage of a memory cell in the first program state (state “0” state in FIG. 18B) is less than a threshold voltage of the memory cell in the second program state (state “1” state in FIG. 18B), and the second program state differs from the first program state by a third number (one) of program states,
wherein:
the second number is greater than the third number; or
the second number (one) is equal to the third number (one).
Regarding claim 4: Cernea ([0153-0161)) teaches the method of claim 1, further comprising:
at the first program stage, after performing the program operation on the second memory cell for the second number of times, inhibiting the second memory cell from being programmed (in a subsequent program operation from state “1” to state “2”, for example, cells having a target state of “1’ are not programmed to state “2”; hence they are inhibited from being further programmed).
Regarding claim 6: Cernea ([0153-0161]) teaches the method of claim 1, further comprising:
at the first program stage, after the first memory cell passes the verification that uses the verify voltage for the target group, inhibiting the first memory cell from being programmed (in a subsequent program operation from state “0” to state “1”, for example, cells having a target state of “0’ are not programmed to state “1”; hence they are inhibited from being further programmed).
Regarding claim 7: Cernea ([0153-0161]) teaches the method of claim 1, further comprising:
at the first program stage, for the memory cells in the target group that do not pass the verification that uses the verify voltage for the target group, continuing performing the program operation, and after performing the program operation, continuing performing the verify operation using the verify voltage for the target group (see section 1.1 of FIG. 17).
Regarding claim 17: Cernea teaches the method of claim 1, wherein the memory cells in the target group have i target program states (state “0”, state “1”, and state “2”, for example), and i is an integer greater than 1 (i = 3), the first program state (state “0”) is a target program state corresponding to the minimum threshold voltage among the i target program states, and the second program state (state “1”) is any one of the i target program states other than the target program state corresponding to the minimum threshold voltage (as illustrated in FIG. 18B of Cernea).
Regarding claim 18: Cernea teaches a memory, comprising:
a memory cell array (200 in FIG. 1) comprising memory cells of a target group;
a plurality of word lines coupled to rows of the memory cell array respectively (word lines are illustrated in FIG. 5A-B);
a plurality of bit lines coupled to memory strings of the memory cell array respectively (bit lines are illustrated in FIG. 5A-B); and
a peripheral circuit (circuits in FIG. 1 other than 200, including row decoder 230A and column decoder 260A) coupled to the memory cell array through the word lines and the bit lines, and configured to: at a first program stage,
perform a program operation on the memory cells of the target group for a first number of times (see 1.1 of FIG. 17, wherein a plurality of program pulses are illustrated and “x program pulses + verifying steps” in FIG. 18B), wherein the memory cells of the target group comprise a first memory cell (a memory that is to be programmed to state “0” as a target state) and a second memory cell (a memory that is to be programmed to state “1” as a target state), wherein a target program state of the first memory cell is a first program state (state “0”), and a target program state of the second memory cell is a second program state (state “1”);
perform a verify operation on the memory cells of the target group using a verify voltage for the target group (see section 1.1 in FIG. 17, wherein verify loops or pules are provided); and
after the second memory cell passes a verification that uses the verify voltage for the target group, perform the program operation on the second memory cell for a second number of times (one time/pulse see section 1.2 in FIG. 17 and FIG. 18B), and inhibit the second memory cell from being verified (no verify loops are executed in 1.2 of FIG. 17; see “without having to verify” in [0155]).
Regarding claim 20: Cernea teaches a memory system, comprising:
a controller (110 in FIG.1); and
a memory (MEMORY ARRAY 200, 230A-B, 250A-B, 260A-B, 270A-B) coupled with the controller and comprising:
a memory cell array (MEMORY ARRAY 200) comprising memory cells of a target group;
a plurality of word lines coupled to rows of the memory cell array respectively (word lines are illustrated in FIG. 5A-B);
a plurality of bit lines coupled to memory strings of the memory cell array respectively (bit lines are illustrated in FIG. 5A-B); and
a peripheral circuit (circuits in FIG. 1 other than 200, including row decoder 230A and column decoder 260A) coupled to the memory cell array through the word lines and the bit lines, and configured to: at a first program stage,
perform a program operation on the memory cells of the target group for a first number of times (see 1.1 of FIG. 17, wherein a plurality of program pulses are illustrated and “x program pulses + verifying steps” in FIG. 18B), wherein the memory cells of the target group comprise a first memory cell (a memory that is to be programmed to state “0” as a target state) and a second memory cell (a memory that is to be programmed to state “1” as a target state), wherein a target program state of the first memory cell is a first program state (state “0”), and a target program state of the second memory cell is a second program state (state “1”);
perform a verify operation on the memory cells of the target group using a verify voltage for the target group (see section 1.1 in FIG. 17, wherein verify loops or pules are provided); and
after the second memory cell passes the verification that uses the verify voltage for the target group, perform the program operation on the second memory cell for a second number of times (one), and inhibit the second memory cell from being verified (no verify loops are executed in 1.2 of FIG. 17; see “without having to verify” in [0155]), and
the memory configured to perform an operation method of the memory, comprising: at the first program stage,
performing the program operation on the memory cells of the target group for the first number of times, wherein the memory cells of the target group comprise the first memory cell and the second memory cell, the target program state of the first memory cell is the first program state, and the target program state of the second memory cell is the second program state (see above);
performing the verify operation on the memory cells of the target group using the verify voltage for the target group (see above); and
after the second memory cell passes the verification that uses the verify voltage for the target group, performing the program operation on the second memory cell for the second number of times, and inhibiting the second memory cell from being verified (see above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cernea (2009/0310421) in view of Hemink et al. (2005/0157552; hereinafter “Hemink”).
Regarding claim 8: Cernea teaches:
during performing the program operation on the second memory cell for the second number of times (one), a program voltage is applied to a selected word line (one programming pulse is seen in FIG. 17; see the pulse labeled “Program State(1)”); and
the memory cells coupled with the selected word line comprising the
memory cells of the target group (FIG. 5B; “The word line coupled to a selected page is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern” in [0016]; “In a preferred embodiment, a page is constituted from a contiguous row of memory cells sharing the same word line.” In [0070]; [0084], [0099-0100]).
Cernea does not specifically teach:
does not specifically teach the method of claim 1, wherein during performing the program operation on the second memory cell for the second number of times, an intermediate voltage or a ground voltage is applied to a bit line coupled with
the second memory cell, and the intermediate voltage being greater than the ground
voltage.
Hemink (FIG. 1, FIG. 2, FIG. 3, FIG. 11, FIG. 15, FIG. 16) teaches programming, wherein during performing a program operation on a memory cell for the a number of times, an intermediate voltage (V1 from t3 to t4 in FIG. 11, for example; [0059-0061]) or a ground voltage (0V; up to t3 in FIG. 1 or FIG. 11, for example; [0059-0061]) is applied to a bit line coupled with the memory cell, and the intermediate voltage being greater than the ground voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Hemink into the device and/or method of Cernea in a manner such that the method of claim 1, wherein during performing the program operation on the second memory cell for the second number of times, a ground voltage would be applied to a bit line coupled with the second memory cell like that taught in FIG. 1 of Hemink, and (regarding claim 9) during performing the program operation on the memory cells of the target group for the first number of times, the program voltage would be applied to the selected word line, and the ground voltage would be applied to the bit line coupled with the second memory cell like that taught in FIG. 1. The motivation to do so would have been to apply a voltage to the bit line that was already known to be suitable for permitting programming of a memory cell as exemplified by Hemink.
Allowable Subject Matter
Claims 5, 11-16, and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY W RADKE whose telephone number is (571)270-1622. The examiner can normally be reached M-F 9-6 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JAY W. RADKE
Primary Examiner
Art Unit 2827
/JAY W. RADKE/Primary Examiner, Art Unit 2827
Prosecution Insights