DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 8-10, 14, and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lopez et al. (US 6,937,102).
In regard to Claim 1:
Lopez discloses, in Figure 2, a power amplifier, comprising:
a depletion mode power transistor (110, Column 3: lines 46-48); and
a level shift circuit (150, 160, 170) configured to generate a level-shifted gate bias control signal (170 output connected to 110, 120, 130) for the depletion mode power transistor based on a gate bias control signal (Column 4: lines 55-62).
In regard to Claim 2:
Lopez discloses, in Figure 2, the power amplifier according to claim 1, wherein the level shift circuit comprises:
a voltage generator (Q3, Q4, Q5);
a voltage reference generator (140); and
a level shifter (170).
In regard to Claim 4:
Lopez discloses, in Figure 2, the power amplifier according to claim 2, wherein the voltage reference generator (140) comprises a resistor voltage divider (R2, R3).
In regard to Claim 8:
Lopez discloses, in Figure 2, the power amplifier according to claim 1, wherein the level shift circuit (170) is configured to expand first voltage levels of the gate bias control signal (170 output) to second voltage levels for the level-shifted gate bias control signal (Column 4: lines 55-62).
In regard to Claim 9:
Lopez discloses, in Figure 2, the power amplifier according to claim 1, wherein the level shift circuit (170) is configured to expand first voltage levels of the gate bias control signal (170 output) to second voltage levels for the level-shifted gate bias control signal based on the gate bias control signal (Column 4: lines 55-62).
In regard to Claim 10:
Lopez discloses, in Figure 2, a level shift circuit for gate bias control, comprising:
a voltage generator (Q3, Q4, Q5) configured to generate a reference voltage based on a supply voltage (Column 4: lines 1-8); and
a level shifter (170) configured to receive a gate bias control signal for a power transistor (110, Column 3: lines 46-48) and to generate a level-shifted gate bias control signal (170 output) for the power transistor based on the reference voltage (Column 4: lines 9-19).
In regard to Claim 14:
Lopez discloses, in Figure 2, the level shift circuit according to claim 10, wherein the level shift circuit (170) is configured to expand first voltage levels of the gate bias control signal (170 output) to second voltage levels for the level-shifted gate bias control signal (Column 4: lines 55-62).
In regard to Claim 16:
Lopez discloses, in Figure 2, a level shift circuit for gate bias control, comprising:
a voltage generator (Q3, Q4) configured to generate a reference voltage (VrefB) based on a supply voltage (Column 4: lines 1-8);
a voltage reference generator (140) configured to generate a reference voltage (Vss) based on the shift voltage (Column 4: lines 43-54); and
a level shifter (170) configured to receive a gate bias control signal (Q5 output) and to generate a level-shifted gate bias control signal (Column 4: lines 9-19).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 5, 11-12, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lopez et al. (US 6,937,102), in view of Raghupathy (US 2017/0063223).
In regard to Claim 3:
All of the claim limitations have been discussed with respect to Claims 1 and 2 above, except for wherein the voltage generator comprises a linear regulator and a charge pump.
Raghupathy discloses, in Figure 5, wherein the voltage generator (502) comprises a linear regulator (501) and a charge pump (503).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the voltage generator taught by Raghupathy with the level shift circuit taught by Lopez, in order to have the quiescent current be zero during regulator operation (Raghupathy ¶ 0047).
In regard to Claim 5:
All of the claim limitations have been discussed with respect to Claims 1 and 2 above, except for wherein: the voltage generator is configured to generate a shifted voltage based on a supply voltage; and the voltage reference generator is configured to provide a reference voltage based on the shifted voltage.
Raghupathy discloses, in Figure 5, wherein: the voltage generator (502) is configured to generate a shifted voltage (507) based on a supply voltage (Vin); and the voltage reference generator (509) is configured to provide a reference voltage (Vclmp) based on the shifted voltage (505).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the voltage generator taught by Raghupathy with the level shift circuit taught by Lopez, in order to have the quiescent current be zero during regulator operation (Raghupathy ¶ 0047).
In regard to Claim 11:
All of the claim limitations have been discussed with respect to Claim 10 above, except for wherein the voltage generator comprises a linear regulator and a charge pump.
Raghupathy discloses, in Figure 5, wherein the voltage generator (502) comprises a linear regulator (501) and a charge pump (503).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the voltage generator taught by Raghupathy with the level shift circuit taught by Lopez, in order to have the quiescent current be zero during regulator operation (Raghupathy ¶ 0047).
In regard to Claim 12:
All of the claim limitations have been discussed with respect to Claim 10 above, except for further comprising: a voltage reference generator, wherein: the voltage generator is configured to generate a shifted voltage based on the supply voltage; and the voltage reference generator is configured to generate the reference voltage based on the shifted voltage.
Raghupathy discloses, in Figure 5, further comprising: a voltage reference generator (502), wherein: the voltage generator (502) is configured to generate a shifted voltage (507) based on a supply voltage (Vin); and the voltage reference generator (509) is configured to provide a reference voltage (Vclmp) based on the shifted voltage (505).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the voltage generator taught by Raghupathy with the level shift circuit taught by Lopez, in order to have the quiescent current be zero during regulator operation (Raghupathy ¶ 0047).
In regard to Claim 17:
All of the claim limitations have been discussed with respect to Claim 16 above, except for wherein the voltage generator comprises a linear regulator and a charge pump.
Raghupathy discloses, in Figure 5, wherein the voltage generator (502) comprises a linear regulator (501) and a charge pump (503).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the voltage generator taught by Raghupathy with the level shift circuit taught by Lopez, in order to have the quiescent current be zero during regulator operation (Raghupathy ¶ 0047).
Allowable Subject Matter
Claims 6-7, 13, 15, and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Tomita (US 2009/0322379) discloses a peak hold circuit includes an input transistor, which is provided with an input signal, and a first hold capacitor, which holds a maximum or minimum value of the input signal. A correction circuit, which corrects the hold voltage held by the first hold capacitor, includes an operational amplifier, which is supplied with the hold voltage, and a correction transistor, which is provided with an output signal of the operational amplifier.
Wilz et al. (US 2017/0237424) discloses a switch bias control circuit includes a level shifter and voltage regulator circuitry configured to receive a voltage reference signal, provide a first voltage output at a first node and provide a second voltage output at a second node, the first node and the second node being at least partially isolated from one another coupling circuitry couples the first node to the level shifter and couples the second node to a negative voltage generator.
Bettencourt et al. (US 9,960, 740) discloses a circuit having an amplifier, comprising: a depletion mode transistor having a source electrode coupled to a reference potential; a drain electrode coupled to a potential more positive than the reference potential; and a gate electrode for coupling to an input signal. The circuit includes a bias circuit, comprising: a current source; and biasing circuitry coupled to the current source and between the potential more positive than the reference potential and a potential more negative than the reference potential. A control circuit is connected to the current source for controlling the amount of current produced by the current source to the biasing circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5.
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/JOHN W POOS/Primary Examiner, Art Unit 2843
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