Prosecution Insights
Last updated: October 02, 2026
Application No. 18/898,293

SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS

Final Rejection §102
Filed
Sep 26, 2024
Priority
Feb 23, 2021 — RE 10-2021-0024098 +2 more
Examiner
TRAN, ANTHAN
Art Unit
2825
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
3m
Est. Remaining
85%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
648 granted / 781 resolved
+15.0% vs TC avg
Minimal +2% lift
Without
With
+2.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
22 currently pending
Career history
804
Total Applications
across all art units

Statute-Specific Performance

§101
1.4%
-38.6% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
35.2%
-4.8% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 781 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s response filed on 07/08/2026 in which claims 1-6 are amended has been entered of record. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ohno (US Pub. 2021/0342242). Regarding claim 1, Fig. 1 of Ohno discloses a semiconductor memory apparatus comprising: a temperature detecting circuit [30] configured to detect a temperature to generate temperature detection information [paragraph 0020, temperature sensor 30 acquires operation temperature of memory 20 or controller 10] and to enable a signal included in the temperature detection information when the temperature is lower than a reference temperature [as discloses in paragraphs 00, the controller 10 control the memory device 20 in two different operations (one of the operation is when the temperature is less than threshold level (paragraph 0027). The enable signal (temperature related) output out sensor 30 helps controller to determine which operation to perform]; a heating control circuit [10] configured to operate in a forcible write mode [any writing mode that does not occurs voluntarily is considered a forcible write mode] when the signal included in the temperature detection information is enabled and to output a command control signal and a heating data signal that toggles [as discloses in paragraphs 0034 to 0037, the controller enable the memory 20 to write cumulative temperature information into 21 base on temperature signal from sensor 30]; and a memory bank circuit [20] configured to store therein the heating data signal based on the command control signal [memory device 20 stores data corresponding to command from controller 10], wherein the memory bank circuit [20] configured to generate heat by forcibly storing the heating data signal [cumulative temperature information] during the forcible write mode [as discloses in paragraph 0037, cumulative temperature is stored in memory section 21 during the forcible write mode (not voluntarily)]. Regarding claim 2, Fig. 1 of Ohno discloses wherein the command control signal includes a write control signal; and wherein the memory bank circuit is configured to perform a write operation including storing the heating data signal [cumulative temperature information, paragraph 0037] based on the write control signal [memory device 20 operates responsive to commands from controller 10]. Regarding claim 3, Fig. 1 Ohno discloses wherein the heating control circuit [10] includes: a write control circuit configured to generate the write control signal when the signal included in the temperature detection information [signal from temperature sensor 30]; and a data providing circuit configured to provide the heating data signal to the memory bank circuit when the signal included in the temperature detection information is enabled [controller 10 control writing operation of memory 20 base on temperature information, as steps S19 in Fig. 2]. Allowable Subject Matter Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 4-6, the prior art does not tech or suggest either alone or in combination: wherein the memory bank circuit is configured to perform, based on the write control signal, a write operation including storing into the memory bank circuit the heating data signal and wherein the heating control circuit is configured to operate in an inversion write mode when the signal included in the temperature detection information is enabled and to output the heating data signal, which is generated by inverting the reading out data and the command control signal repeatedly from the memory bank circuit. Response to Arguments Applicant's arguments filed 07/08/2026 have been fully considered but they are not persuasive. Applicant argues that Ohno does not teach or suggest “a temperature detecting circuit configured to detect a temperature to generate temperature detection information and to enable a signal included in the temperature detection information when the temperature is lower than a reference temperature and a heating control circuit configured to operate in a forcible write mode when the signal included in the temperature detection information is enabled and to output a command control signal and a heating data signal that toggles”. As aforementioned in the new rejection, Ohno does teach the new added limitations (see above). Therefore, all applicant’s arguments were fully considered, they are not persuasive. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ANTHAN TRAN/Primary Examiner, Art Unit 2825
Read full office action

Prosecution Timeline

Sep 26, 2024
Application Filed
Apr 08, 2026
Non-Final Rejection mailed — §102
Jul 08, 2026
Response Filed
Sep 24, 2026
Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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A NON-VOLATILE READ REFRESH OPERATION COMPRISING DISCHARGING A PLURALITY OF WORD LINES
5y 0m to grant Granted Sep 22, 2026
Patent 12744081
BINARY NEURAL NETWORK HARDWARE APPARATUS
2y 7m to grant Granted Sep 22, 2026
Patent 12744089
SEMICONDUCTOR MEMORY DEVICE
1y 11m to grant Granted Sep 22, 2026
Patent 12738332
MEMORY DEVICE WITH IMPROVED THRESHOLD VOLTAGE DISTRIBUTION AND OPERATING METHOD THEREOF
3y 2m to grant Granted Sep 15, 2026
Patent 12725648
MEMORY APPARATUS, REFRESH CONTROL CIRCUIT AND ROW HAMMER REFRESH METHOD
3y 0m to grant Granted Sep 01, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
85%
With Interview (+2.4%)
2y 3m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 781 resolved cases by this examiner. Grant probability derived from career allowance rate.

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