DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ohno (US Pub. 2021/0342242).
Regarding claim 1, Fig. 1 of Ohno discloses a semiconductor memory apparatus comprising:
a temperature detecting circuit [30] configured to detect a temperature to generate temperature detection information [temperature signal to circuit 12];
a heating control circuit [12] configured to provide, based on the temperature detection information, a command control signal and a heating data signal that toggles [command and data input to memory device 20]; and
a memory bank circuit [20] configured to store therein the heating data signal based on the command control signal [memory device 20 stores data corresponding to command from controller 10],
wherein the memory bank circuit [20] is configured to generate heat through a toggling operation [since memory device operates under electrical current, every time memory device 20 operates to read/write data, it inherently generates heat].
Regarding claim 2, Fig. 1 of Ohno discloses wherein the command control signal includes a write control signal, and wherein the memory bank circuit is configured to perform a write operation of storing therein the heating data signal based on the write control signal [memory device 20 operates responsive to commands from controller 10].
Regarding claim 3, Fig. 1 Ohno discloses wherein the heating control circuit [10] includes: a write control circuit configured to generate the write control signal based on the temperature detection information [signal from temperature sensor 30]; and a data providing circuit configured to provide, based on the temperature detection information, the heating data signal to the memory bank circuit [controller 10 control writing operation of memory 20 base on temperature information, as steps S19 in Fig. 2].
Regarding claim 4, Fig. 1 of Ohno discloses wherein the command control signal includes read and write (read/write) control signals [controller 10 controls both read and write operations of memory 20], wherein the memory bank circuit is configured to perform, based on the read control signal, a read operation of reading out data stored in the memory bank circuit [step S12 in Fig. 2], and wherein the memory bank circuit is configured to perform, based on the write control signal, a write operation of storing into the memory bank circuit the heating data signal [step S19 in Fig. 2], which is inverted from the read-out data from the memory bank circuit.
Regarding claim 5, Fig. 1 of Ohno discloses wherein the heating control circuit includes: a read/write control circuit configured to generate the read/write control signals based on the temperature detection information [step S12 and step S19]; and a data inverting circuit configured to generate, based on the temperature detection information, the heating data signal, which is inverted from the read-out data from the memory bank circuit [as shows in Fig. 2 and Fig. 1, memory read/write operations are performed in response to temperature signal from senser 30].
Regarding claim 6, Fig. 2 of Ohno discloses wherein, in an inversion write mode, a pair of the read operation on the data stored in the memory bank circuit [20, Fig. 1] and the write operation on the heating data signal is performed an even number of times [both read and write operations can perform an even number of times (for example 2 times)].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825