DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al. (US Pub.: 2019/0312772) in view of Sureka (US Pub.: 2018/0262413), Li et al. (US Pub.: 2011/0153935), and Warkentin et al. (US Patent 11,263,019).
As per claim 1, Zhao teaches/suggests a method for resource configuration, comprising: having a Non-Uniform Memory Access, NUMA, architecture of a processor socket ([0014]; [0025]; and [0034]); operating with acceleration resources of an accelerator including a plurality of acceleration resource elements, the plurality of acceleration resource elements operating accordingly ([0014]; [0025]; [0027] and [0034]); and having the plurality of acceleration resource elements operate with the processor socket, wherein acceleration resources in acceleration resource elements operate accordingly ([0014]; and [0025]-[0029]); operating with the acceleration resource elements; determine a target acceleration resource element for a core when accessing the accelerator ([0014]; [0025]-[0029]; and [0052]) (Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; and [0084]-[0086]).
Zhao does not teach the method comprising:
obtaining, by a firmware during boot process, an indication for a number of Non-Uniform Memory Access, NUMA, nodes;
dividing, by the firmware, resources into resource queues based on the number of NUMA nodes, the resources queues presented as independent devices by using the firmware; and
associating, by the firmware, each of the plurality of resource queues to a respective NUMA node included in the processor, wherein a number of resources in each resource queue is proportional to a number of cores of the associated NUMA node and is configurable via an interface of the firmware;
generating, by the firmware, description information representing an association between the resource queues and the respective NUMA nodes;
wherein the description information is stored in a system description table accessible by an operating system or an application during runtime, and the description information is used to determine a resource queue within a NUMA node.
Sureka teaches/suggests a method comprising: operating by a firmware during boot process (e.g. associated with resource being allocated during pre-boot, initialization, power, or reboot time by firmware: [0020]; [0035]); operating by the firmware, resources presented as independent devices by using the firmware (e.g. associated with firmware allocating resource, wherein the resource can be independent from one another: [0020]-[0022]; and [0035]); and operating by the firmware and is configurable via an interface of the firmware (e.g. associated with firmware allocating resource via corresponding interface: [0020]; [0035]) ([0004]; [0015]-[0024]; [0031]-[0035]; and [0050]-[0055]).
Li teaches/suggests a method for resource configuration, comprising: obtaining an indication for a number of Non-Uniform Memory Access, NUMA, nodes (e.g. associate with a number of nodes being determined in step 410 of Fig. 4: [0028]); dividing resources into resource queues based on the number of NUMA nodes, the resources queues operating accordingly (e.g. associated with storage resources being divided into queue pair to corresponding node: [0028]); and associating each of the plurality of resource queues to a respective NUMA node included in the processor (e.g. associated with allocating queue pair to corresponding node for use by the corresponding node’s cores: [0027]-[0028]), wherein a number of resources in each resource queue is proportional to a number of cores of the associated NUMA node (e.g. associated with a number of queue pairs being allocated to a node with a corresponding number of core(s): [0017]-[0018]; [0027]-[0028]); and an association between the resource queues and the respective NUMA nodes (e.g. associated with the queue pair being allocated to corresponding node for use by the corresponding node’s cores: [0027]-[0028]); operating with a resource queue within a NUMA node (e.g. associated with operating with the queue pair(s): [0017]-[0018]; [0027]-[0028]) (Fig. 1; Fig. 4; and [0012]-[0028]).
Warkentin teaches/suggests a method comprising: generating, by the firmware, description information representing (e.g. associated with generating ACPI definitions to include in ACPI tables: col. 5, ll. 24-29); and wherein the description information is stored in a system description table accessible by an operating system or an application during runtime, and the description information is used to determine (e.g. associated with OS accessing ACPI tables when running to determine associated hardware: col. 4, ll. 11-17; col. 4, ll. 58-62; col. 5, ll. 24-30) (Fig. 4-5; and col. 3, l. 25 to col. 7, l. 63).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Sureka’s firmware operations, Li’s resource allocation and Warkentin’s firmware operations into Zhao’s method for the benefit of providing better resource utilization (Sureka, [0017]), reducing total number of allocation in the system (Li, [0013]), and generating ACPI tables that are needed by the various layers of OS/hypervisor (Warkentin, col. 2, ll. 7-11; and col. 4, ll. 1-17) to obtain the invention as specified in claim 1.
As per claim 2, Zhao, Sureka, Li and Warkentin teach/suggest all the claimed features of claim 1 above, where Zhao and Li further teach/suggest the method comprising wherein obtaining the indication comprises: presenting an entry for setting the number of NUMA nodes; and obtaining the indication through the entry (Zhao, [0029]) (Zhao, Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; [0084]-[0086]; and Li , Fig. 1; Fig. 4; [0012]-[0028]), wherein it would have been obvious to one of ordinary skilled in the art to use information at corresponding entry for dynamically setting the number of nodes.
As per claim 3, Zhao, Sureka, Li and Warkentin teach/suggest all the claimed features of claim 1 above, where Zhao and Li further teach/suggest the method further comprising: allocating the plurality of processor cores associated with the processor socket to respective NUMA nodes based on the number of NUMA nodes (Zhao, Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; [0084]-[0086]; and Li , Fig. 1; Fig. 4; [0012]-[0028]), wherein it would have been obvious to one of ordinary skilled to further implement the above claimed features as the devices are dynamically identified and allocated.
As per claim 4, Zhao, Sureka, Li and Warkentin teach/suggest all the claimed features of claim 1 above, where Zhao , Li and Warkentin further teach/suggest the method further comprising: wherein the description information indicates at least a respective identifier of at least one acceleration resource queue associated with the respective NUMA nodes (Zhao, Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; [0084]-[0086]; Li , Fig. 1; Fig. 4; [0012]-[0028]; and Warkentin, Fig. 4-5; col. 3, l. 25 to col. 7, l. 63), wherein it would have been obvious to one of ordinary skilled to further implement the above claimed features.
As per claim 5, Zhao, Sureka, Li and Warkentin teach/suggest all the claimed features of claim 4 above, where Zhao, Sureka, Li and Warkentin further teach/suggest the method further comprising: in response to at least one core within a first node of the respective NUMA nodes being about to use the accelerator, determining a first acceleration resource queue of the at least one acceleration resource queue allocated to the first node based on the description; and causing the at least one core to be accelerated with acceleration resources in the first acceleration resource queue (Zhao, Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; [0084]-[0086]; Sureka, [0004]; [0015]-[0024]; [0031]-[0035]; [0050]-[0055]; Li , Fig. 1; Fig. 4; [0012]-[0028]; and Warkentin, Fig. 4-5; col. 3, l. 25 to col. 7, l. 6), wherein it would have been obvious to one of ordinary skilled to further implement the above claimed features.
As per claim 6, Zhao, Sureka, Li and Warkentin teach/suggest all the claimed features of claim 4 above, where Zhao, Sureka, Li and Warkentin further teach/suggest the method further comprising: in response to the number of NUMA nodes being changed, adjusting the association of the at least one acceleration resource queue with the respective NUMA nodes; and updating the description based on an adjusted association relationship (Zhao, Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; [0084]-[0086]; Sureka, [0004]; [0015]-[0024]; [0031]-[0035]; [0050]-[0055]; Li , Fig. 1; Fig. 4; [0012]-[0028]; and Warkentin, Fig. 4-5; col. 3, l. 25 to col. 7, l. 6), wherein it would have been obvious to one of ordinary skilled to further implement the above claimed features.
As per claim 7, claim 7 is rejected in accordance to the same rational and reasoning as the above rejection of claim 1, where Zhao, Sureka, Li and Warkentin further teach/suggest the electronic device, comprising: at least one processing unit; and at least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, the instructions, when executed by the at least one processing unit, causing the electronic device to perform a method for resource configuration (Zhao, Fig. 7; [0084]-[0086]) (Zhao, Fig. 1; Fig. 7; [0014]; [0017]; [0025]-[0040]; [0052]-[0061]; [0084]-[0086]; Sureka, [0004]; [0015]-[0024]; [0031]-[0035]; [0050]-[0055]; Li , Fig. 1; Fig. 4; [0012]-[0028]; and Warkentin, Fig. 4-5; col. 3, l. 25 to col. 7, l. 6).
As per claims 8-12, claims 8-12 are rejected in accordance to the same rational and reasoning as the above rejection of claims 2-6.
As per claims 13-18, claims 13-18 are rejected in accordance to the same rational and reasoning as the above rejection of claims 1-6.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 October 20, 2025
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