DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
2. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-11 are rejected under 35 U.S.C. 103 as obvious over Watakabe et al. (US 2018/0122835 A1), hereinafter as W1, in view of Son et al. (US 2018/0366586 A1), hereinafter as S1
4. Regarding Claim 1, W1 discloses a display device (see in particular Figs. 1-6, 23-25 see [0086] “The combination of the LTPS TFT and the TAOS TFT explained in the first embodiment and in the second embodiment can be applied to an organic EL display device”) comprising:
a substrate (element 100, see [0088] “TFT substrate 100”) including a display region (element 10, see [0087] “display area 10”) in which a plurality of pixels (see [0086] “organic EL layers” plural layers for plural pixels) are disposed;
a first thin film transistor (see Fig. 6 left transistor, see [0062] “LTPS TFT”), a second thin film transistor (see Fig. 6 right transistor, see [0062] “TAOS TFT”), wherein the first thin film transistor and the second thin film transistor each include an active layer, a gate electrode, a source electrode and a drain electrode (first transistor active layer element 102, gate electrode element 104, source electrode left element 115, drain electrode right element 115, see [0046, 0062]) (second transistor active layer element 107, gate electrode element 111, source electrode left element 116, drain electrode right element 116, see [0047, 0062]), and the active layer of the first thin film transistor is made of low temperature poly silicon (LTPS) (see [0046] “LTPS 102”) and the active layer of the second thin film transistor is made of an oxide semiconductor (see [0006, 0047] “an oxide semiconductor, which is amorphous and optically transparent, is called TAOS (Transparent Amorphous Oxide Semiconductor)”);
a first dielectric layer (element 106, see [0048] “interlayer insulating film 106”) disposed on the gate electrode of the first thin film transistor, wherein the second thin film transistor is disposed on the first dielectric layer (see Fig. 6); and
an anode (see Fig. 25 element 211 and [0090] “lower electrode 211, which works as an anode”), an organic layer (element 212, see [0090] “organic EL layer 212”), and a cathode (element 213, see [0090] “upper electrode 213, which works as a cathode”).
W1 does not explicitly disclose a capacitor disposed in each of the plurality of pixels; a connection electrode connected to the source electrode or the drain electrode of the first thin film transistor; a planarization layer disposed on the connection electrode; the anode, organic layer, and cathode disposed on the planarization layer; wherein the source electrode and the drain electrode of the second thin film transistor, and the connection electrode include at least two of same material.
S1 discloses (see in particular Fig. 3A) a capacitor (element CST, see [0095] “storage capacitor Cst”); a connection electrode (element 217, see [0099] “connection electrode 217’) connected to the source electrode or the drain electrode of the first thin film transistor (drain element 215 of the first transistor element 210, see [0094] “first TFT 210 includes the first active layer 211 including polycrystalline silicon”); a planarization layer (element 119, see [0102] “planarization layer 119”) disposed on the connection electrode (see Fig. 3A); the anode, organic layer, and cathode disposed on the planarization layer (see Fig. 3A elements 410, 420, 430 on element 119 and see [0102]); wherein the source electrode and the drain electrode of the second thin film transistor (elements 225S, 225D of element 220, see [0060] “second TFT 220 may include a second active layer 221 including an oxide semiconductor”), and the connection electrode include at least two of same material (see Fig. 4L and [0131] “each of the second electrode 225 including the source electrode 225S and the drain electrode 225D, the connection electrode 217, and the second conductive layer 320 may have a three-layer structure in which Ti, Al and Ti are sequentially stacked on one another”).
The capacitor, connection electrode and conductive material as taught by S1 is incorporated as a capacitor, connection electrode and conductive material for each of the display pixels of W1, wherein the combination further discloses the capacitor disposed in each of the plurality of pixels.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of S1 with W1 because the combination provides a storage capacitor without increased additional space (see S1 [0095]) and the connection electrode and material provides mechanical, and electrical connection which may also be utilized in a flexible area (see S1 [0142]).
5. Regarding Claim 2, W1, S1 disclose the display device of claim 1, wherein the source electrode and the drain electrode of the second thin film transistor, and the connection electrode have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (see S1 Fig. 4L and [0131] “each of the second electrode 225 including the source electrode 225S and the drain electrode 225D, the connection electrode 217, and the second conductive layer 320 may have a three-layer structure in which Ti, Al and Ti are sequentially stacked on one another”).
6. Regarding Claim 3, W1, S1 disclose the display device of claim 2, wherein the source electrode and the drain electrode of the first thin film transistor have a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti) (see S1 [0122] “each of the first electrode 215 and the first conductive layer 310 may have a three-layer structure in which Ti, Al and Ti are sequentially stacked on one another”).
7. Regarding Claim 4, W1, S1 disclose the display device of claim 1, further comprising: a buffer layer (see W1 element 101, see [0044] “undercoat 101 is often formed by a laminated film of silicon oxide (SiO) and silicon nitride (SiN)”) disposed between the substrate, and the active layer of the first thin film transistor (see W1 Fig. 6).
8. Regarding Claim 5, W1, S1 disclose the display device of claim 1, wherein (see S1) the capacitor includes a first electrode (portion of element 213), and a second electrode (element CE2), wherein the first electrode is disposed on a same layer as the gate electrode of the first thin film transistor (see S1 Fig. 3A), and the second electrode is disposed on the first dielectric layer and overlaps with the first electrode (see S1 Fig. 3A).
9. Regarding Claim 6, W1, S1 disclose the display device of claim 1, further comprising: an encapsulating portion (see W1 Fig. 25 element 214, see [0090] “protective film 214”) disposed on the cathode.
10. Regarding Claim 7, W1, S1 disclose the display device of claim 5, wherein the second electrode is disposed on and contacts a same layer as the active layer of the second thin film transistor (see S1 Fig. 3A on a lower surface and contacts a same layer element 114 as the active layer element 221 of the second thin film transistor element 221).
11. Regarding Claim 8, W1, S1 disclose the display device of claim 5, wherein the second electrode is disposed on a same layer as the active layer of the second thin film transistor (see S1 Fig. 3A both on the layer of element 113).
12. Regarding Claim 9, W1, S1 disclose the display device of claim 1, further comprising: a display element including the anode, the organic layer, and the cathode (see W1 Fig. 25), wherein the first thin film transistor is configured to drive the display element (see W1 [0007] “the TFT of LTPS has high carrier mobility, thus a driving circuit can be formed by the TFT of LTPS”).
13. Regarding Claim 10, W1, S1 disclose the display device of claim 1, wherein the buffer layer is made of mono-layer of silicon nitride (SiNx) or silicon oxide (SiOx) (see W1 element 101, see [0044] “undercoat 101 is often formed by a laminated film of silicon oxide (SiO) and silicon nitride (SiN)”), or multi-layer of silicon nitride (SiNx) and silicon oxide (SiOx).
14. Regarding Claim 11, W1, S1 disclose the display device of claim 1, further comprising: a second dielectric layer disposed between the gate electrode of the second thin film transistor, and the planarization layer (see W1 Fig. 6 element 112, see [0056] “interlayer insulating film 112”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached on Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
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/SAMUEL PARK/Examiner, Art Unit 2818
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