DETAILED ACTION
This non-final action is responsive to the following communications: application filed on 09/26/2024.
Claims 1-20 are pending. Claims 1, 10, and 18 are independent.
Restriction Requirement Withdrawn
Previously set restriction requirements (dated 05/06/2026) are being withdrawn based on the following reasons:
persuasive arguments against restriction requirements dated 07/06/2026 (see Remarks pages 6-7); and
claim amendments of claim 10 dated 07/06/2026 presented by applicant.
Applicant’s arguments are found persuasive and previous restriction requirements are being withdrawn.
Claims 1-20 are pending.
Examiner Notes
Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety. Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
4. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 01/16/2026. This IDS has been considered.
Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Interpretation
5. A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) See rejection for interpretation of functional terms or terms defining relations.
Drawings Objections
6. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim language (crossed-out limitations) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. A timings diagram illustrating various clock signals, CA, address, delay/ offset introduction is suggested and would be sufficient to illustrate the limitations. None of the current figures 1-6 illustrate the crossed-out limitations in sufficient details. For example, see US 2010/0220536 A1 Fig. 4, Fig. 6 illustrate clock delay and associated parameters in sufficient details that allows proper examination of claim limitations, functions. See also US 2009/0116598 A1 Figure 1 illustrations as example. Drawings in the application lack adequate illustration of the claimed features.
Regarding independent claim 1, a memory controller, comprising:
a clock source configured to output a clock signal to a plurality of ranks; and
a level trainer comprising circuitry configured to:
write a delta between the second clock delay and the first clock delay in a register in the second rank, and
Regarding independent claim 10, a method, comprising:
write a delta between the second clock delay and the first clock delay in a register in the second rank, and
Regarding independent claim 18, a memory system, comprising:
a plurality of ranks, each comprising a plurality of memory chips; and
a memory controller configured to:
write a delta between the second clock delay and the first clock delay in a register in the second rank, and
Corrected drawing sheets in compliance with 37 CFR 1.121 (d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121 (d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
7. Claims 1, 10, and 18 (and associated dependent claims inclusive of claims 1-20) are objected to because they are not clearly readable on drawings, and subject to plural interpretations. See Drawing objections and highlighted limitations above in section 6.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1-2, 4-5, 8-11, 13-14, and 18-19 is/are rejected under 35 U.S.C. 103 as being obvious over UM et al. (US 2024/0046975 A1), in view of Richards et. A1 (US 2025/0166690 A1) and Coteus et al. (US 2010/0220536 A1).
Regarding independent claim 1, UM teaches a memory controller (Fig. 9: 2100 “memory controller”), comprising:
a clock source (see Fig. 3: 1130 “clock generator”; para [0067]) configured to output a clock signal (Fig. 9: WCKt, WCKc) to a plurality of ranks (Fig. 9: 2200 “Rank0”, 2300 “Rank1”. See para [0099]); and
a level trainer (“timing controller” and “delay control logic” combined. See Fig. 2: 1140, Fig. 4: 1290) comprising circuitry configured to:
perform level training (para [0102]: “data bus training” on 2200. See “…memory controller 2100 may perform data bus training for each of the memory devices 2200 and 2300.…”) to generate a first clock delay for a first rank of the plurality of ranks (para [0102]: WCKt/ WCKc to DQ margin is determined for 2200. see “…margin of the data signal DQ of each of the memory devices 2200 and 2300 may be checked based on a result of data bus training…”. Assume 2200 has more than or equal to threshold margin and requires zero delay adjustment to WCKt/ WCKc),
perform level training (para [0102], para [0107]) to generate a second clock delay for a second rank of the plurality of ranks (para [0102]: WCKt/ WCKc to DQ margin is determined for 2300. Assume 2300 has less than threshold margin and requires equivalent delay adjustment to WCKt/ WCKc),
wherein the first clock delay (zero delay since margin is at or above threshold) is less than the second clock delay (equivalent delay due to less margin),
write a delta between the second clock delay and the first clock delay in a register in the second rank (para [0102]: “…variable delay lines 2240 and 2340 of the data clock signals WCKt and WCKc may be set using fuses or mode register sets...”. para [0077]: information associated with clock delay is stored in mode register), and
transmit the clock signal to both the first and second ranks that is delayed by the first clock delay (Fig. 9: zero delay is used to transmit WCKt/ WCKc to 2220, 2320 of the ranks),
wherein the second rank is configured to further delay the clock signal using the delta written in the register (Fig. 9 in context of para [0107], para [0105]: based on data bus training delay line 2340 is adjusted to add delay to resolve DQ margin and skew between ranks).
UM is silent with respect to “…write a delta between the second clock delay and the first clock delay in a register in the second rank…”
Richards teaches storing clock offs delta (para [0033]: storing clock offsets) in a register in the second rank (para [0033]: mode register with each memory device can store clock offset)
Coteus teaches write a delta between the second clock delay and the first clock delay in a register in the second rank (Fig. 7 ranks; see Fig. 14 in context of para [0080]: using digital bits to store delay in mode register).
UM, Richards, and Coteus are in the same field of endeavor of clock delay and clock adjustment scheme in DDR memory system for read/ write and they are in analogous field of art.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Richards and Coteus into the teachings of UM such that method to store clock offsets in register can be employed in memory system in order to improve clock/ data/ command alignment (Richards, para [0016]) and in order to reduce power consumption, improve performance (Coteus para [0056]).
Regarding claim 2, UM, Richards, and Coteus teach the memory controller of claim 1. UM teaches wherein the clock source is configured to output a data clock (WCK) (para [0067]: WCKt, WCKc from controller) and a command clock (CK) (para [0067]: CK-t, CK-c from controller) to the plurality of ranks (see Fig. 9, Fig. 2), wherein the clock signal is the WCK (Fig. 9, para [0067]).
Regarding claim 4, UM, Richards, and Coteus teach the memory controller of claim 1. UM teaches wherein the first clock delay is a minimum clock delay for all the plurality of ranks (See zero delay applicable for all ranks. See also in context of paragraphs [0046], [0055], [0062]; and figures 1-3: delay size or unit delay applicable).
Regarding claim 5, UM, Richards, and Coteus teach the memory controller of claim 1. UM teaches wherein the level trainer is configured to: detect whether the delta exceeds a maximum offset (misalignment between DQ and WCKt/ WCKc is within tolerance is expected for the controller to function for “training” properly as understood by ordinary skill in the art).
Regarding claim 8, UM, Richards, and Coteus teach the memory controller of claim 1. Coteus teaches wherein the register is a mode register (MR) (Coteus para [0080]: “mode register”).
Regarding claim 9, UM, Richards, and Coteus teach the memory controller of claim 1. UM teaches wherein the plurality of ranks comprises Low-Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM) (UM para [0051]: LPDDR SDRAM).
Regarding independent claim 10, UM, Richards, and Coteus teach a method, comprising:
performing level training to generate a first clock delay for a first rank of a plurality of ranks of memory chips,
performing level training to generate a second clock delay for a second rank of the plurality of ranks of memory chips,
wherein the first clock delay is less than the second clock delay,
write a delta between the second clock delay and the first clock delay in a register in the second rank, and
transmit a clock signal to both the first and second ranks that is delayed by the first clock delay,
wherein the second rank is configured to further delay the clock signal using the delta written in the register.
(This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding claim 11, UM, Richards, and Coteus teach the method of claim 10, further comprising: transmitting a WCK and a CK to the plurality of ranks of memory chips, wherein the clock signal is the WCK. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 2, and is therefore rejected for the same reasons as claim 2).
Regarding claim 13, UM, Richards, and Coteus teach the method of claim 10, further comprising: detecting that the first clock delay is a minimum clock delay for all the plurality of ranks of memory chips.
Regarding claim 14, UM, Richards, and Coteus teach the method of claim 10, further comprising: detecting whether the delta exceeds a maximum offset.
Regarding independent claim 18, UM, Richards, and Coteus teach a memory system, comprising:
a plurality of ranks, each comprising a plurality of memory chips; and
a memory controller configured to:
perform level training to generate a first clock delay for a first rank of the plurality of ranks,
perform level training to generate a second clock delay for a second rank of the plurality of ranks,
wherein the first clock delay is less than the second clock delay,
write a delta between the second clock delay and the first clock delay in a register in the second rank, and
transmit a clock signal to both the first and second ranks that is delayed by the first clock delay,
wherein the second rank is configured to further delay the clock signal using the delta written in the register. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 1, and is therefore rejected for the same reasons as claim 1).
Regarding claim 19, UM, Richards, and Coteus teach the memory system of claim 18, wherein the memory controller comprises a clock source configured to output a data clock (WCK) and a command clock (CK) to the plurality of ranks, wherein the clock signal is the WCK. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 2, and is therefore rejected for the same reasons as claim 2).
12. Claims 3, 12, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over UM et al. (US 2024/0046975 A1), Richards et. A1 (US 2025/0166690 A1) and Coteus et al. (US 2010/0220536 A1), in further view of Kim-6598 et al (US 2009/0116598 A1).
Regarding claim 3, UM, Richards, and Coteus teach the memory controller of claim 2. UM Fig. 6 teaches WCK has a frequency that is a multiple of the CK.
UM, Richards, and Coteus are silent with respect to remaining provisions of this claim.
Kim-6598 teaches wherein performing level training comprises performing WCK2CK level training, wherein the WCK has a frequency that is a multiple of the CK (Frequency of the data clock is twice as much as that of the system clock; and when the data clocks (WCK, WCK#) are activated, the clock alignment training (WCK2CK TRAINING), in which the phases of the data clocks (WCK, WCK#) and system clocks (CK, CK#) are aligned, is performed within a predetermined time. See paragraphs [0009], [0021]; and Figures 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Kim-6598 into the teachings of UM, Richards, and Coteus such that WCK2CK level training can be employed in memory system in order to support functions of high-speed system operations (Kim-6598 Abstract).
Regarding claim 12, UM, Richards, Coteus, and Kim-6598 teach the method of claim 11, wherein performing level training comprises performing WCK2CK level training, wherein the WCK has a frequency that is a multiple of the CK. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3).
Regarding claim 20, UM, Richards, Coteus, and Kim-6598 teach the memory system of claim 19, wherein performing level training comprises performing WCK2CK level training, wherein the WCK has a frequency that is a multiple of the CK. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 3, and is therefore rejected for the same reasons as claim 3).
13. Claims 6, and 15 is/are rejected under 35 U.S.C. 103 as being obvious over UM et al. (US 2024/0046975 A1), Richards et. A1 (US 2025/0166690 A1) and Coteus et al. (US 2010/0220536 A1), in further view of Lee (US 9,646,675 B1).
Regarding claim 6, UM, Richards, and Coteus teach the memory controller of claim 5. They are silent with respect to remaining provisions of this claims as it pertains to training control scheme.
Lee teaches upon detecting that the delta exceeds the maximum offset (col. 2, lines 8-29: error due to voltage drop in memory device), the level trainer is configured to stop a training process (end an iteration or loop of training) and report a training error (col. 2, lines 8-29: “reflecting a training error”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lee into the teachings of UM, Richards, and Coteus such that memory device timing/ clock training can be employed in memory system in order to “improve training accuracy” (Lee col. 2, lines 8-29).
Regarding claim 15, UM, Richards, Coteus, and Lee teach the method of claim 14, further comprising: upon detecting that the delta exceeds the maximum offset: stopping a training process, and reporting a training error. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 6, and is therefore rejected for the same reasons as claim 6)
14. Claims 7, and 16-17 is/are rejected under 35 U.S.C. 103 as being obvious over UM et al. (US 2024/0046975 A1), Richards et. A1 (US 2025/0166690 A1) and Coteus et al. (US 2010/0220536 A1), in further view of KIM-7016 et al (US 20230147016 A1).
Regarding claim 7, UM, Richards, and Coteus teach the memory controller of claim 1. They are silent with respect to MRS details.
KIM-7016 teaches wherein the memory controller is configured to operate in an Always on Mode as a Mode Register Set (MRS) option (para [0108], para [0114], para [0038]: LPDDR5 and JEDEC mode register set usage. LPDDR5 SDRAM supports WCK Always on Mode as a Mode Register Set MRS option, which is also referred to as a WCK free running mode).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of KIM-7016 into the teachings of UM, Richards, and Coteus such that LPDDR5 MRS structure, functionality can be employed in memory system in order to improve training speed.
Regarding claim 16, UM, Richards, Coteus, and Kim-7016 teach the method of claim 10, wherein performing level training is performed with a memory controller coupled to the plurality of ranks of memory chips operating in an Always on Mode as a MRS option. (This claim is drafted as in method format, substantially identical to the functionality recited in claim 7, and is therefore rejected for the same reasons as claim 7)
Regarding claim 17, UM, Richards, Coteus, and Kim-7016 teach the method of claim 10, wherein the register is a MR (Kim-7016 para [0108], para [0114], para [0038]).
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure:
Shaeffer (US 2012/0311371 A1): Shaeffer teaches the first clock offset value and the second clock offset value are different (in context of para [0116]], para [0040]: clock rate and phase is adjusted for slow device and fast device by utilizing PLL or rate select circuit, divider and thus the adjustments are different). Shaeffer teaches the apparatus of claim 1, wherein the first memory device is configured to determine the speed at which the first memory device is operating based upon a clock speed of the clock signal (Fig. 1: slower or, faster clock is input to memory device which is further altered by PLL/ rate select circuit, divider. Thus PLL/ rate select circuit, divider utilizes determined input clock speed to generate device specific clocks). Tung et al. (US 2012/0239870 A1): Tung teaches a clock tree (Tung Fig. 5 and Fig. 6 disclosure where it is taught that inserting delays and drivers after clock source generates clock tree which can be propagated to memory devices and components). Limitation of clock tree is further supported by Chang para [0008] where it is taught that clock tree circuit being used in memory module and configured to generate delayed clock signal. Chang et al. (US 2019/0187744 A1): disclosure is applicable for all claims.
Janzen (US 2005/0108590 A1): Janzen teaches a method at a memory device (para [0013], Fig. 3: 300 “memory device”), comprising: selecting, at the memory device, a clock offset value (para [0028]: “trimmable delays” and Fig. 4) from a plurality of clock offset values based at least in part on a mode register of the memory device (Fig. 4 in context of para [0028]: “…Selection of which one of the trimmable delays 411, 412, 413 to activate is through the use of the CAS latency value LAT(A), LAT(B), LAT(C) programmed in the mode register 335 of the control logic…”. See also para [0025], para [0027], para [0028]); and offsetting a clock signal (Fig. 4: CLKDEL is output after offset) received at the memory device based at least in part on the selected clock offset value (para [0028]: “…the trimmable delays…provide an output clock signal having a respective delay…”. See also para [0027]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached 7:00 am-4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
Prosecution Insights