DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, 8-9, 12, 15-16, 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Schreiber et al. (US 2024/0220856 A1, “Schreiber”).
As to claims 1, 8, 15, Schreiber discloses a processor, comprising:
one or more circuits to use two or more neural network encoders to encode two or more different portions of a set of information to be used by two or more neural networks, each comprising one of the two or more neural network encoders, respectively (machine learning models 204 may include multiple encoder neural networks that separately process shape data in different formats to generate corresponding embeddings, para. 0030, Fig. 3A).
As to claims 2, 9, 16, Schreiber discloses: wherein the one or more circuits further use the two or more neural network encoders to encode a same input to be used by the two or more neural networks (two or more neural network encoders 310(1)-310(X) are used to encode a same input shape 301; Fig. 3A).
As to claims 5, 12, 18, Schreiber discloses: wherein individual ones of the two or more neural networks are executed by respective ranks of one or more graphics processor units (GPUs) that store encoded values of the two or more different portions of the set of information in respective key-value caches (processor(s) may be a GPU, para. 0020).
Allowable Subject Matter
Claims 3-4, 6-7, 10-11, 13-14, 17, 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Raman et al. (US 2021/0374345 A1) teach encoding two or more tuples of input sequences using two or more neural networks (Fig. 1).
Olszewski (US 2002/0136319 A1) teach a plurality of neural networks which receive a corresponding one of a plurality of segments.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Stella L Woo whose telephone number is (571)272-7512. The examiner can normally be reached Monday - Friday, 8 a.m. to 5 p.m.
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STELLA L. WOO
Primary Examiner
Art Unit 2693
/Stella L. Woo/ Primary Examiner, Art Unit 2693
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