Prosecution Insights
Last updated: October 04, 2026
Application No. 18/898,675

SEMICONDUCTOR TEST DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §102§103
Filed
Sep 27, 2024
Priority
Apr 01, 2024 — RE 10-2024-0044310 +2 more
Examiner
HE, AMY
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Olum Material Corporation
OA Round
2 (Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
8m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
435 granted / 535 resolved
+13.3% vs TC avg
Minimal +4% lift
Without
With
+4.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
10 currently pending
Career history
552
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
47.5%
+7.5% vs TC avg
§102
32.9%
-7.1% vs TC avg
§112
9.6%
-30.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 535 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 7-10 and 12-13 are rejected under 35 U.S.C. 102(a)(1), 102(a)(2) as being anticipated by Akram et al. (U. S. Patent 6,107,109). As for claim 1, Akram et al. discloses a semiconductor test device (see the interconnect 40 or 40A in the wafer test system 80 in Figs. 7-7C, 8; also see the interconnect shown in Figs. 1A-1D), which can be interposed between semiconductor memories (52), or between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising: a membrane portion (See 10 in Figs. 1A-1D; 10C in Fig. 8) comprising a plurality of aperture patterns (see the plurality of recesses 12 and/or openings 30 in Figs. 1A-1D) in a thickness direction; and a holder portion (116 in Fig. 7) having a hollow region (122) and connected to an edge of the membrane portion (10; 10C), wherein the membrane portion comprises a metal thin film portion (see Fig. 3B, the portion including the metal conductive layer 26/26A and the conductive members 34/34A that covers the sidewalls of opening 30) having the plurality of aperture patterns (12, 30) and an insulating layer portion (24) with an insulating material coated on a surface of the metal thin film portion, wherein neighboring aperture patterns (12, 30) are insulated from each other (i.e., insulated by insulating layer 24), and a conductive thin film layer (34, 26) is formed on side surfaces of each of the aperture patterns (i.e., the conductive members 34 can be metal layers that cover the inside surfaces or sidewalls of the opening 30, see col. 6, lines 25-37 and Fig. 3B; and metal layer 26 covers the sidewalls of the recess 12), wherein the metal thin film portion comprises a first metal thin film portion in which the aperture pattern has a first width and a second metal thin film portion in which the aperture pattern has a second width that is narrower than the first width (i.e., as shown in Fig. 3B, the first metal thin film portion is the portion of the membrane 10A covered with the metal conductive layer 26A with a wider aperture width, and the second metal thin film portion is the portion of the membrane 10A covered with the conductive members 34A that covers the sidewalls of the opening 30 with a second narrower aperture width as shown in Fig. 3B), and wherein a portion of the second metal thin film portion that protrudes further in a lateral direction than the first metal thin film portion is provided as a cantilever portion (i.e., the second metal thin film portion with a narrower aperture width of opening 30 is seen protruding in a lateral direction and is provided as the cantilever portion; see Fig. 3B). As for claim 7, Akram et al. discloses the semiconductor test device of claim 1, wherein the metal thin film portion is made of at least one of Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy or nickel (i.e. the metal thin film layer 26 can be made of nickel, see col. 5, lines 31-35). As for claim 8, Akram et al. discloses the semiconductor test device of claim 1, wherein the conductive thin film layer (34, 26) comprises at least one of Cu, Ag, Au, Pt or Pd (see col. 5, lines 31-35 and col. 6, lines 25-28). As for claim 9, Akram et al. discloses the semiconductor test device of claim 1, wherein the conductive thin film layer (26) is further formed in a horizontal direction at a top of the side surfaces of each of the aperture patterns, or is further formed in the horizontal direction at a bottom of the side surfaces of each of the aperture patterns (i.e., 26 is formed in a horizontal direction at a top of each recess 12, as shown in Fig. 1A-1D). As for claims 10 and 12, Akram et al. discloses the semiconductor test device of claim 1, wherein the hollow region (opening 122 between the holders 116 in Fig. 7) of the holder portion (116) serves as a space for accommodating the semiconductor memory (52) and each of the aperture patterns (12, 30) corresponds to each of a plurality of micro bumps (18) formed on a lower portion of the semiconductor memory, wherein an area of the semiconductor memory corresponds to a size of one cell, a size of a plurality of cells (see Fig. 7), or a size of a silicon wafer, and a horizontal area of the hollow region of the holder portion is larger than the of the semiconductor memory (52). As for claim 13, Akram et al. discloses the semiconductor test device of claim 12, wherein a width of the aperture pattern is 5 to 100µm (i.e., see col. 5, lines 64-65). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Akram et al. (U. S. Patent 6,107,109). As for claim 20, Akram et al. discloses the semiconductor test device of claim 1, wherein the membrane portion comprises the metal thin film portion having a first thickness (see the thickness shown in Fig. 3B) and the insulating layer portion (24 in Figs. 1 and 3) with an insulating material coated on a surface of the metal thin film portion, the holder portion (116 in Fig. 7) has a second thickness and is integrally connected to the edge of the membrane portion (see Fig. 7). Akram et al. does not specifically disclose that the second thickness is thicker than the first thickness, and the metal thin film portion and the holder portion are made of the same metal material. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akram et al. to disclose that holder thickness is thicker than the first thickness of the metal thin film portion for the purpose of providing a more secure and stronger support. Moreover, the person would also find it obvious to use the same metal material for both the metal thin film portion and the holder portion to minimize the thermal and mechanical stress caused by temperature changes. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Akram et al. (U. S. Patent 6,107,109), in view of McQuade et al. (U. S. Pub. 2003/0146769). As for claim 14, Akram et al. discloses the semiconductor test device of claim 1, wherein the holder portion (116) is formed from a silicon wafer, the metal thin film portion (26) is formed on the silicon wafer by electroforming (col. 5, lines 31—46). Still referring to claim 14, Akram does not specifically disclose that the metal thin film portion includes an Invar or Super Invar material. McQuade et al. discloses using an invar material with low coefficient of thermal expansion, for reducing the temperature effects (abstract; [0050]). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akram to use invar material with low coefficient of thermal expansion, for the metal thin film portion, in order to reduce they temperature effects when testing the semiconductor device (see abstract and [0050 of McQuade et al.) As for claim 15, Akram et al. in view of McQuade et al. discloses the semiconductor test device of claim 14, as discussed above. Akram et al. does not specifically disclose wherein a connection portion containing Ni and Si, or a connection portion containing Fe, Ni, and Si, is interposed between the holder portion and the metal thin film portion. It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akram to use any conventional connection layer containing desired material such as Ni, Si, or Fe, Ni and Si for the purpose of easily or securely connecting the holder and the metal thin film portion. Response to Arguments Applicant's arguments filed July 22, 2026 have been fully considered but they are not persuasive. In response to applicant’s argument that Arkam et al. does not teach or suggest a first metal thin film portion and a second thin film portion, and the second metal thin film portion provided as a cantilever portion, the examiner asserts that Arkam et al. does clearly disclose those features in Fig. 3B. Fig. 3B of Arkam et al. is reproduced below: PNG media_image1.png 181 632 media_image1.png Greyscale Fig. 3B clearly shows wherein the metal thin film portion comprises a first metal thin film portion (see the top arrow shown above) in which the aperture pattern has a first width and a second metal thin film portion(see the bottom arrow shown above) in which the aperture pattern has a second width that is narrower than the first width (i.e., the first metal thin film portion is the portion of the membrane 10A covered with the metal conductive layer 26A with a wider aperture width, and the second metal thin film portion is the portion of the membrane 10A covered with the conductive members 34A that covers the sidewalls of the opening 30 with a second narrower aperture width); and wherein a portion of the second metal thin film portion that protrudes further in a lateral direction than the first metal thin film portion is provided as a cantilever portion (i.e., the second metal thin film portion with a narrower aperture width of opening 30 is seen protruding in a lateral direction and is considered as the cantilever portion). In response to applicant’s argument that “the conductive members of Akram occupy the opening”, the examiner asserts that Fig 3B clearly disclose an alternative embodiment wherein the conductive member 34A does not occupy the opening 30, instead, it cover just the sidewalls of the opening 30 as shown in Fig. 3B above (see also col. 6, lines 35-37). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY HE whose telephone number is (571)272-2230. The examiner can normally be reached 9:00am--5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMY HE/ Primary Examiner, Art Unit 2858
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Prosecution Timeline

Sep 27, 2024
Application Filed
Apr 22, 2026
Non-Final Rejection mailed — §102, §103
Jul 22, 2026
Response Filed
Aug 10, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
86%
With Interview (+4.3%)
2y 8m (~8m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 535 resolved cases by this examiner. Grant probability derived from career allowance rate.

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