Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, species II in the reply filed on April 02, 2026 is acknowledged.
The elected Group I, species II (i.e., seventh embodiment as shown in Fig. 18) is directed to claims 1, 7-10, 14-15 and 18.
Clams 12-13, 16-17, 19-20 and 22-25 are withdrawn from consideration since they do not read on the elected Group I, species II:
Claims 12 and 13 are clearly directed to the nonelected species I (Fig. 3) which requires an electrical connection path 130 formed from a top to a bottom.
Claims 16-17 and 19-20 are clearly directed to the nonelected species III (Fig. 25), which requires a conductive cantilever portion.
Claims 22-25 are directed to the nonelected group II.
Applicant is reminded to cancel all the nonelected claims 12-13, 16-17, 19-20 and 22-25 in the next response.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 7-10 are rejected under 35 U.S.C. 102(a)(1), 102(a)(2) as being anticipated by Akram et al. (U. S. Patent 6,107,109).
As for claim 1, Akram et al. discloses a semiconductor test device (see the interconnect 40 or 40A in the wafer test system 80 in Figs. 7-7C, 8; also see the interconnect shown in Figs. 1A-1D), which can be interposed between semiconductor memories (52), or between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising:
a membrane portion (See 10 in Figs. 1A-1D; 10C in Fig. 8) comprising a plurality of aperture patterns (see the plurality of recesses 12 and/or openings 30 in Figs. 1A-1D) in a thickness direction; and
a holder portion (116 in Fig. 7) having a hollow region (122) and connected to an edge of the membrane portion (10; 10C),
wherein the membrane portion comprises a metal thin film portion (i.e., the portion of the interconnect contact 32, including a metal conductive layer 26) having the plurality of aperture patterns (12, 30) and an insulating layer portion (24) with an insulating material coated on a surface of the metal thin film portion,
wherein neighboring aperture patterns (12, 30) are insulated from each other (i.e., insulated by insulating layer 24), and a conductive thin film layer (34, 26) is formed on side surfaces of each of the aperture patterns (i.e., the conductive members 34 can be metal layers that cover the inside surfaces or sidewalls of the opening 30, see col. 6, lines 25-37 and Fig. 3B; and metal layer 26 covers the sidewalls of the recess 12),
wherein each of the aperture patterns (12, 30) has a shape with a width decreasing from the top to the bottom (see the decreasing width of the recess 12 and 30) thereof, or a shape with the narrowest width at a center thereof, and
a plurality of micro bumps (bumps 18) formed on a lower portion of the semiconductor memory are guided into the aperture patterns (12, 30) at least along side surfaces of the aperture patterns and make contact with the conductive thin film layer (34, 26).
As for claim 7, Akram et al. discloses the semiconductor test device of claim 1, wherein the metal thin film portion is made of at least one of Invar, Super Invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy or nickel (i.e. the metal thin film layer 26 can be made of nickel, see col. 5, lines 31-35).
As for claim 8, Akram et al. discloses the semiconductor test device of claim 1, wherein the conductive thin film layer (34, 26) comprises at least one of Cu, Ag, Au, Pt or Pd (see col. 5, lines 31-35 and col. 6, lines 25-28).
As for claim 9, Akram et al. discloses the semiconductor test device of claim 1, wherein the conductive thin film layer (26) is further formed in a horizontal direction at a top of the side surfaces of each of the aperture patterns, or is further formed in the horizontal direction at a bottom of the side surfaces of each of the aperture patterns (i.e., 26 is formed in a horizontal direction at a top of each recess 12, as shown in Fig. 1A-1D).
As for claim 10, Akram et al. discloses the semiconductor test device of claim 1, wherein the hollow region (opening 122 between the holders 116 in Fig. 7) of the holder portion (116) serves as a space for accommodating the semiconductor memory (52) and each of the aperture patterns (12, 30) corresponds to each of a plurality of micro bumps (18) formed on a lower portion of the semiconductor memory.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Akram et al. (U. S. Patent 6,107,109), in view of McQuade et al. (U. S. Pub. 2003/0146769).
As for claim 14, Akram et al. discloses a semiconductor test device (see the interconnect 40 or 40A in the wafer test system 80 in Figs. 7-7C, 8; also see the interconnect shown in Figs. 1A-1D), which can be interposed between semiconductor memories (52), or between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising:
a membrane portion (See 10 in Figs. 1A-1D; 10C in Fig. 8) comprising a plurality of aperture patterns (see the plurality of recesses 12 and/or openings 30 in Figs. 1A-1D) in a thickness direction; and
a holder portion (116 in Fig. 7) having a hollow region (122) and connected to an edge of the membrane portion (10; 10C),
wherein the membrane portion comprises a metal thin film portion (i.e., the portion of the interconnect contact 32, including a metal conductive layer 26) having the plurality of aperture patterns (12, 30) and an insulating layer portion (24) with an insulating material coated on a surface of the metal thin film portion,
wherein neighboring aperture patterns (12, 30) are insulated from each other (i.e., insulated by insulating layer 24), and a conductive thin film layer (34, 26) is formed on side surfaces of each of the aperture patterns (i.e., the conductive members 34 can be metal layers that cover the inside surfaces or sidewalls of the opening 30, see col. 6, lines 25-37 and Fig. 3B; and metal layer 26 covers the sidewalls of the recess 12), wherein the holder portion (116) is formed from a silicon wafer, the metal thin film portion (26) is formed on the silicon wafer by electroforming (col. 5, lines 31—46).
Still referring to claim 14, Akram does not specifically disclose that the metal thin film portion includes an Invar or Super Invar material.
McQuade et al. discloses using an invar material with low coefficient of thermal expansion, for reducing the temperature effects (abstract; [0050]).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akram to use invar material with low coefficient of thermal expansion, for the metal thin film portion, in order to reduce they temperature effects when testing the semiconductor device (see abstract and [0050 of McQuade et al.)
As for claim 15, Akram et al. in view of McQuade et al. discloses the semiconductor test device of claim 14, as discussed above.
Akram et al. does not specifically disclose wherein a connection portion containing Ni and Si, or a connection portion containing Fe, Ni, and Si, is interposed between the holder portion and the metal thin film portion.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akram to use any conventional connection layer containing desired material such as Ni, Si, or Fe, Ni and Si for the purpose of easily or securely connecting the holder and the metal thin film portion.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Akram et al. (U. S. Patent 6,107,109).
As for claim 18, Akram et al. discloses a semiconductor test device (see the interconnect 40 or 40A in the wafer test system 80 in Figs. 7-7C, 8; also see the interconnect shown in Figs. 1A-1D), which can be interposed between semiconductor memories (52), or between a semiconductor memory and an interposer, to perform a test of an electrical connection, comprising:
a membrane portion (See 10 in Figs. 1A-1D; 10C in Fig. 8) comprising a plurality of aperture patterns (see the plurality of recesses 12 and/or openings 30 in Figs. 1A-1D) in a thickness direction; and
a holder portion (116 in Fig. 7) having a hollow region (122) and connected to an edge of the membrane portion (10; 10C),
wherein the membrane portion comprises a metal thin film portion (i.e., the portion of the interconnect contact 32, including a metal conductive layer 26) having the plurality of aperture patterns (12, 30) and an insulating layer portion (24) with an insulating material coated on a surface of the metal thin film portion,
wherein neighboring aperture patterns (12, 30) are insulated from each other (i.e., insulated by insulating layer 24), and a conductive thin film layer (34, 26) is formed on side surfaces of each of the aperture patterns (i.e., the conductive members 34 can be metal layers that cover the inside surfaces or sidewalls of the opening 30, see col. 6, lines 25-37 and Fig. 3B; and metal layer 26 covers the sidewalls of the recess 12), and
wherein the metal thin film portion (i.e., the portion of the interconnect contact 32, including a metal conductive layer 26) comprises a first metal thin film portion in which the aperture pattern has a first width and a second metal thin film portion in which the aperture pattern has a second width (i.e., the first metal thin film portion is the portion with the first recess 12 and opening 30, and the second metal thin film portion is the portion with the second recess 12 and opening 30 in Fig. 1A-1D).
Still referring to claim 18, Akram et al. does not specifically disclose that the second width is narrower than the first width.
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to modify Akram to use a second width for the second metal thin film portion, that is narrower or larger than the first width, in order to properly match the shape and size of a different external contact/bumps 18 located in the second metal thin film portion (see Akram, col. 4, lines 46-61).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY HE whose telephone number is (571)272-2230. The examiner can normally be reached 9:00am--5:00pm.
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/AMY HE/ Primary Examiner, Art Unit 2858
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