DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-9, 11-15 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park US 2008/0174023 A1.
Regarding claims 1, 5-9 and 11-15, Park discloses:
A semiconductor package (Fig. 23C) comprising:
an interconnection structure (300) in which at least one insulating layer and at least one interconnection layer are alternately stacked (para 0108; e a multi-layer PCB or film package substrate which has a circuit pattern on an organic material substrate);
a semiconductor chip (100) including a plurality of pads (130), the semiconductor chip at least partially overlapping with the interconnection structure in the vertical direction;
a plurality of bumps (314) between the plurality of pads and the interconnection structure;
a peripheral pad portion (120/180) at least a portion of which is on a side surface of the semiconductor chip, the peripheral pad portion being electrically connected to the semiconductor chip by a surface thereof that is opposing the semiconductor chip; and
a peripheral connection portion (316) electrically connecting the peripheral pad portion and the interconnection structure to each other.
(claim 5) a first peripheral pad portion (170); a second peripheral pad portion (120b) (Fig. 17B).
(claim 6) a plurality of peripheral pads (120/180); a plurality of connection wirings (316) (Fig. 23A).
(claim 7) Fig. 15A/15B; para 0114, 318 triangular.
(claim 8) para 0060.
(claim 9) Fig. 23C.
(claim 11) para 0129; bumps (solder) versus peripheral connection portion (metal).
(claim 12) para 0131; Fig. 23C in view of Fig. 1; para 0006.
(claims 13-15) Fig. 23C in view of para 0133; and Figs. 17C and 17D.
Regarding claim 19, Park discloses:
A semiconductor package (Fig. 23C) comprising:
an interconnection structure (300) in which at least one insulating layer and at least one interconnection layer are alternately stacked (para 0108; e a multi-layer PCB or film package substrate which has a circuit pattern on an organic material substrate);
a semiconductor chip (100) including a plurality of pads (130), the semiconductor chip at least partially overlapping with the interconnection structure in the vertical direction;
a plurality of bumps (314) between the plurality of pads and the interconnection structure;
a peripheral connection portion (120/180) at least partially surrounding the plurality of bumps (in view of Fig. 23A),
wherein the semiconductor chip includes
a semiconductor substrate above the plurality of pads; and
a device layer between the plurality of pads and the semiconductor substrate,
wherein the device layer includes a chip interconnection layer having a portion electrically connected to the plurality of pads, and
another portion of the chip interconnection layer is exposed to a side surface of the semiconductor chip and is electrically connected to the peripheral connection portion (para 0131; Fig. 23C in view of Fig. 1; para 0006).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 10, 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park US 2008/0174023 A1 in view of Lee US 2022/0254732 A1.
Regarding claims 2-4, Park does not disclose:
(claim 2) further comprising: an underfill portion between the interconnection structure and the semiconductor chip, the underfill portion at least partially surrounding the plurality of bumps, wherein the peripheral connection portion at least partially extends along a surface of the underfill portion; (claim 3) further comprising: an encapsulant above the interconnection structure and at least partially encapsulating the semiconductor chip, wherein the peripheral connection portion is between the underfill portion and the encapsulant; and (claim 4) wherein the peripheral connection portion is in contact with the underfill portion and with the encapsulant.
Lee discloses a publication from a similar field of endeavor in which:
(claim 2) further comprising: an underfill portion (205) between the interconnection structure (201) and the semiconductor chip (202), the underfill portion at least partially surrounding the plurality of bumps (solder bumps between 201 and 202); (claim 3) further comprising: an encapsulant (209) above the interconnection structure and at least partially encapsulating the semiconductor chip, wherein the peripheral connection portion is between the underfill portion and the encapsulant (Fig. 2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the underfill portion and encapsulation of Lee within the similar structure, albeit a metal for EMI shielding, of Park such that the peripheral connection portion at least partially extends along a surface of the underfill portion and (claim 4) wherein the peripheral connection portion is in contact with the underfill portion and with the encapsulant to protect the solder bumps and chip package from external/environmental damage.
Regarding claim 10, Park does not disclose:
wherein a separation distance between the peripheral connection portion and a bump closest to the peripheral connection portion, among the plurality of bumps, is longer than a separation distance between the plurality of bumps.
Lee discloses a publication from a similar field of endeavor in which:
wherein a separation distance between wiring portion (206) and a bump (solder bumps between 201 and 202) closest to the peripheral connection portion, among the plurality of bumps, is longer than a separation distance between the plurality of bumps (Fig .2).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the same claimed distance requirements between the peripheral connection portion and the solder bumps of Park as shown by Lee to further protect/secure the solder bumps and chip placement from potential delamination and damage.
Regarding claims 16-18, Park discloses:
A semiconductor package (Fig. 23C) comprising:
an interconnection structure (300) in which at least one insulating layer and at least one interconnection layer are alternately stacked (para 0108; e a multi-layer PCB or film package substrate which has a circuit pattern on an organic material substrate);
a semiconductor chip (100) including a plurality of pads (130), the semiconductor chip at least partially overlapping with the interconnection structure in the vertical direction;
a plurality of bumps (314) between the plurality of pads and the interconnection structure; and
a peripheral connection portion (316)
extending from a position lower than that of an upper surface of the semiconductor chip to the interconnection structure (Fig. 23C), and
electrically connecting the semiconductor chip and the interconnection structure to each other.
Park does not disclose:
an underfill portion between the interconnection structure and the semiconductor chip, the underfill portion at least partially surrounding the plurality of bumps; and a peripheral connection portion extending along a surface of the underfill portion.
Lee discloses a publication from a similar field of endeavor in which:
an underfill portion (205) between the interconnection structure (201) and the semiconductor chip (202), the underfill portion at least partially surrounding the plurality of bumps (solder bumps between 201 and 202);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the underfill portion of Lee within the similar structure, albeit a metal for EMI shielding, of Park such that the peripheral connection portion at least partially extends along a surface of the underfill portion to protect the solder bumps while connecting the peripheral connection portions to the substrate using a shorter distance.
(claim 17) a first peripheral pad portion (170); a second peripheral pad portion (120b) (Fig. 17B).
(claim 18) Fig. 15A/15B; para 0114, 318 triangular.
Regarding claim 20, Park discloses:
further comprising: a peripheral pad portion (120/180) electrically connected to the another portion of the chip interconnection layer and to the peripheral connection portion (Fig. 23C).
Park does not disclose:
an underfill portion at least partially surrounded by the peripheral connection portion, the underfill portion at least partially surrounding the plurality of bumps.
Lee discloses a publication from a similar field of endeavor in which:
an underfill portion (205) at least partially surrounded by the peripheral connection portion (206), the underfill portion at least partially surrounding the plurality of bumps (solder bumps between 201 and 202).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ the underfill portion of Lee within the similar structure, albeit a metal for EMI shielding, of Park such that the peripheral connection portion at least partially extends along a surface of the underfill portion to protect the solder bumps while connecting the peripheral connection portions to the substrate using a shorter distance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30.
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/ERROL V FERNANDES/Primary Examiner, AU 2893
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