Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made that application is a continuation of International Application No. PCT/JP2023/012690 filed on March 28, 2023, which claims priority from Japanese Patent Application No. 2022-057359 filed on March 30, 2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 27, 2024, is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Naoto (JP 2004111415 A) and Shinozaki (US 2021/0091796 A1).
With respect to claim 1, Naoto teaches:
a substrate (insulating substrate 5) having a first main surface (top) and a second main surface (bottom) facing each other and a through-hole (through hole 11) extending through the substrate (5) from the first main surface to the second main surface;
a first electronic component (semiconductor chip 3);
and a second electronic component (substrate 7),
wherein the second electronic component is disposed inside the through-hole of the substrate (See Fig 2),
the first electronic component (3) is disposed to extend over the first main surface of the substrate (top of 5) and the second electronic component (7),
the first electronic component (3) is connected to the first main surface (top) of the substrate (5) with a first connection member (protruding electrode 41 attached to terminal 30b) interposed therebetween,
the second electronic component (7) is connected to the first electronic component (3) with a second connection member (41 attached to terminal 30a) interposed therebetween,
Naoto fails to teach:
A high-frequency module comprising:
and the high-frequency module is configured to supply a first direct current signal to the second electronic component through the first connection member, the first electronic component, and the second connection member.
Shinozaki teaches an analogous device that is a multi-chip radio frequency module. Naoto teaches a general method of creating a multi-chip module that is not limited to a specific application. It would be obvious to modify the multi-chip module packaging structure of Naoto with the teachings of Shinozaki that a multi-chip module can be applied to a high-frequency module application to meet the limitation:
A high-frequency module (radio frequency module 1):
and the high-frequency module is configured to supply a first direct current signal to the second electronic component (7 of Naoto, analogous to output matching circuit 30 of Shinozaki) through the first connection member (protruding electrode 41 attached to terminal 30b or Naoto, analogous to portion of current path from input 111 to amplifier 11 of Shinozaki), the first electronic component (power amplifier 11), and the second connection member (protruding electrode 41 attached to terminal 30a or Naoto output of power amplifier 11 of Shinozaki).
It would be obvious to combine Naoto with the teachings of Shinozaki under the rationale “ Combining Prior Art Elements According to Known Methods To Yield Predictable Results.” The Graham factual inquiries of this rational are:(1) a finding that the prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference;
(2) a finding that one of ordinary skill in the art could have combined the elements as claimed by known methods, and that in combination, each element merely performs the same function as it does separately;
(3) a finding that one of ordinary skill in the art would have recognized that the results of the combination were predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
Naoto and Shinozaki teach all elements of the claimed invention as described above. One of ordinary skill in the art could have applied the teachings of Shinozaki to make a high-frequency module in a multi chip module with the teachings of Naoto to arrange the chips as claimed as the circuit of the high frequency module would be expected to operate the same in the geometry of Naoto and that the benefits of the layout of Naoto would be applicable regardless of application of the chips. One of ordinary skill in the art would recognize that the combination would be predictable as chip packaging layouts and interconnection schemes can generally be applied to many different device applications. The ordinary artisan would be motivated to make such a modification for the purpose of making a high frequency module with a reduced size.
With respect to claim 2, Naoto further teaches:
further comprising:
a third electronic component (semiconductor chip 2) disposed to extend over the first main surface (top) of the substrate (5) and the second electronic component (7) and adjacent to the first electronic component (3) with a space interposed therebetween,
wherein the third electronic component (2) is connected to the first main surface (top) of the substrate (5) with a third connection member (41 attached to 20b) interposed therebetween,
the second electronic component (7) is connected to the third electronic component (2) with a fourth connection (41 attached to 20a) member interposed therebetween,
Shinozaki teaches an analogous device that is a multi-chip radio frequency module. Naoto teaches a general method of creating a multi-chip module that is not limited to a specific application. It would be obvious to modify the multi-chip module packaging structure of Naoto with the teachings of Shinozaki that a multi-chip module can be applied to a high-frequency module application to meet the limitation:
and the high-frequency module is configured to supply a second direct current signal (output of power amplifier 12) to the second electronic component (30) through the third connection member (41 attached to 20a of Naoto, analogous to output of 12 of Shinozaki), the third electronic component (12), and the fourth connection member (41 attached to 20b, analogous to input from 112 to 12 of Shinozaki).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Naoto in view of Shinozaki as explained above.
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Naoto (JP 2004111415 A) and Shinozaki (US 2021/0091796 A1) as applied to claim 2 above and further in view of Chiang (US 2024/0178187 A1).
With respect to claim 3, Naoto/Shinozaki teach all limitations of claim 1 upon which claim 3 depends. Naoto/Shinozaki fails to teach:
a mounting substrate facing the second main surface of the substrate,
wherein the first electronic component has a portion overlapping with the second electronic component and a portion overlapping with the first main surface of the substrate in plan view,
and the portion of the first electronic component overlapping with the first main surface of the substrate is connected to the mounting substrate with a through-via interposed therebetween.
Chiang teaches:
a mounting substrate (substrate 10) facing the second main surface (bottom) of the substrate (first packaging layer 15),
wherein the first electronic component (second chip 12) has a portion overlapping with the second electronic component (first connection chip 13) and a portion overlapping with the first main surface (top) of the substrate (15) in plan view,
and the portion of the first electronic component (12) overlapping with the first main surface of the substrate (15) is connected to the mounting substrate (10) with a through-via (conductive column 14) interposed therebetween.
Naoto/Shinozaki discloses the claimed invention except for the mounting substrate on the second surface connected to the first electronic component with through vias. Chiang teaches that it is known to connect a first component on a first side of a substrate to a mounting substrate by through vias through the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Naoto/Shinozaki by Chiang for the purpose of connecting the electrical components to external connections. See MPEP 2144.
With respect to claim 7, Naoto/Shinozaki teach all limitations of claim 2 upon which claim 7 depends. Naoto/Shinozaki fails to teach:
a mounting substrate facing the second main surface of the substrate,
wherein the first electronic component has a portion overlapping with the second electronic component and a portion overlapping with the first main surface of the substrate in plan view,
and the portion of the first electronic component overlapping with the first main surface of the substrate is connected to the mounting substrate with a through-via interposed therebetween.
Chiang teaches:
a mounting substrate (substrate 10) facing the second main surface (bottom) of the substrate (first packaging layer 15),
wherein the first electronic component (second chip 12) has a portion overlapping with the second electronic component (first connection chip 13) and a portion overlapping with the first main surface (top) of the substrate (15) in plan view,
and the portion of the first electronic component (12) overlapping with the first main surface of the substrate (15) is connected to the mounting substrate (10) with a through-via (conductive column 14) interposed therebetween.
Naoto/Shinozaki discloses the claimed invention except for the mounting substrate on the second surface connected to the first electronic component with through vias. Chiang teaches that it is known to connect a first component on a first side of a substrate to a mounting substrate by through vias through the substrate. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Naoto/Shinozaki by Chiang for the purpose of connecting the electrical components to external connections. See MPEP 2144.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Naoto (JP 2004111415 A) and Shinozaki (US 2021/0091796 A1) and Chiang (US 2024/0178187 A1) as applied to claim 3 above and further in view of Horita (US 2022/0021404 A1) and Teeter (US 2015/0200189 A1).
With respect to claim 4, Naoto/Shinozaki/Chiang teaches all limitations of claim 3 upon which claim 4 depends. Naoto/Shinozaki/Chiang fails to teach:
wherein the first electronic component has a driver-stage amplifier configured to amplify an input high-frequency signal and output a first amplified signal,
and a power-stage amplifier configured to amplify the first amplified signal and output a second amplified signal,
the portion of the first electronic component overlapping with the second electronic component is provided with the driver-stage amplifier,
and the portion of the first electronic component overlapping with the first main surface of the substrate is provided with the power-stage amplifier.
Horita teaches:
wherein the first electronic component (first power amplifier 9a) has a driver-stage amplifier ([0033] “first amplifying unit 91a is, for example, a driver-stage amplifying unit”) configured to amplify an input high-frequency signal and output a first amplified signal,
and a power-stage amplifier ([0033] “the second amplifying unit 92a is, for example, a power-stage amplifying unit”) configured to amplify the first amplified signal and output a second amplified signal,
Naoto/Shinozaki discloses the claimed invention except for the component having a driver-stage amplifier and power-stage amplifier. Horita teaches that it is known to mount an amplifier module including a driver-stage and power-stage amplifier as the first electronic module. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Naoto/Shinozaki by Horita to house the driver stage amplifier and power stage amplifier in a single chip, as taught by Horita in order to reduce the space and wiring required for the amplifiers. See MPEP 2144.
Naoto/Shinozaki/Horita differs from the claimed invention in the arrangement of portions of the first electronic component over the second electronic component and substrate. Teeter teaches that it is known to stack dies with an offset so that the hot portions of the power amplifier die do not interfere with the operation of other dies. It would be obvious over the teachings of Teeter and routine experimentation to arrange the electronic components so that the hottest parts of the first electronic component are over the substrate, not the second component, to meet the limitations:
the portion of the first electronic component overlapping with the second electronic component is provided with the driver-stage amplifier,
and the portion of the first electronic component overlapping with the first main surface of the substrate is provided with the power-stage amplifier.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to make the portions overlapped as claimed, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70. The ordinary artisan would be motivated to optimize the layout of the portions of the chips for the purpose of improving the wiring layout of the interconnections between the chips and because Teeter teaches in Fig. 11 that locations of hot spots in the power amplifiers should be taken into consideration when designing the package.
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Naoto (JP 2004111415 A) and Shinozaki (US 2021/0091796 A1) as applied to claim 2 above and further in view of Chikita (US 2020/0359507 A1).
With respect to claim 5, Naoto/Shinozaki teaches all limitations of claim 2 upon which claim 5 depends. Naoto/Shinozaki fails to teach:
a fourth electronic component disposed on the second main surface of the substrate.
Chikita teaches in Fig. 3:
a fourth electronic component (inductor 32a) disposed on the second main surface (bottom) of the substrate (mounting substrate 60).
Note: Chikita’s inductor 31b is considered analogous to the first electronic component, switch IC 10 is analogous to the second electronic component, and filter 21 is analogous to the third electronic component.
Naoto/Shinozaki discloses the claimed invention except electronic components mounted on both sides of the substrate. Chikita teaches that it is known to mount components to both sides of a substrate in a high frequency module. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Naoto/Shinozaki by Chikita for the purpose of reducing the lengths of coupling lines within the device to reduce propagation loss. See MPEP 2144.
With respect to claim 6, Chikita further teaches:wherein the fourth electronic component (32a) is disposed to extend over the second main surface (bottom) of the substrate (60) and the second electronic component (10),
the fourth electronic component (32a) is connected to the second electronic component (10) with a fifth connection member interposed therebetween,
and the fourth electronic component (32a) is connected to the third electronic component (21) with the fifth connection member, the second electronic component (10), and the fourth connection member interposed therebetween (see annotated Fig. 3 below).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Naoto in view of Shinozaki and Chikita as explained above.
PNG
media_image1.png
460
687
media_image1.png
Greyscale
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.M.W./ Examiner, Art Unit 2897
/JACOB Y CHOI/ Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights