Prosecution Insights
Last updated: October 21, 2026
Application No. 18/898,848

FERROELECTRIC SEMICONDUCTOR THIN FILM AND METHOD OF FORMING THE SAME AND TRANSISTOR AND MEMORY DEVICE AND INTEGRATED CIRCUIT

Non-Final OA §102§103
Filed
Sep 27, 2024
Priority
Oct 16, 2023 — RE 10-2023-0137942 +1 more
Examiner
RODRIGUEZ, MICHAEL P
Art Unit
1712
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Adrc Co. Kr
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
501 granted / 683 resolved
+8.4% vs TC avg
Strong +29% interview lift
Without
With
+29.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
32 currently pending
Career history
715
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
23.7%
-16.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 683 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Information Disclosure Statement The information disclosure statements (IDS) submitted on 04 June 2025 and 23 October 2025 have been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 1. Claims 1-2 and 7-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ashok et al.; Growth of In2Se3 Thin Films Prepared by the Pneumatic Spray Pyrolysis Method for Thin Film Solar Cells Applications; 2020 17th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE). Mexico City, Mexico. November 11-13, 2020; (“Ashok”). With regard to Claims 1, and 7-15, Ashok teaches a method of forming a semiconductor film comprising preparing a precursor solution including indium precursor and a selenium precursor, and performing spray pyrolysis of the precursor solution on a substrate to obtain a thin film thereof, including a polycrystalline γ-In2Se3 layer, and usage thereof in solar cell electronic devices (see Abstract; Experimental Details Sections A-B and FIG. 1 at Pg. 2; Results and Discussions Section B at Pg. 3). Ashok thus teaches the preparation of the claimed precursor materials, and deposition thereof using the claimed process steps thereby obtaining a thin film comprising polycrystalline γ-In2Se3. Properties associated with the deposited film are understood to necessarily derive therefrom. With regard to Claim 2, Ashok teaches substrate temperatures within the claimed range (see Experimental Details Section B and Results and Discussions Section A at Pg. 2). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 2. Claims 5-6 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ashok. With regard to Claim 5, Ashok teaches a process for depositing a film thickness of 1 µm (see Experimental Details Section B at Pg. 2). It would have been obvious to one of ordinary skill in the art at the time the inventio was filed to have conducted multiple deposition operations in order to achieve a desired film thickness. With regard to Claims 6 and 16-20, Ashok is directed to usage of films in solar cell applications and that the films are otherwise widely used in a variety of semiconductor devices, including transistors, memory units, and integrated circuits (see Introduction at Pg. 1). It would have thus been obvious to one of ordinary skill in the art at the time the invention was filed to have employed the γ-In2Se3 films of Ashok to produce devices as claimed. 3. Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Ashok as applied to Claim 1, and further in view of Ates et al.; Annealing and Light Effect on Optical and Electrical Properties of Evaporated Indium Selenide Thin Films; Physica E 40 (2008) 2709-2713; (“Ates”). With regard to Claims 3-4, Ashok does not expressly teach annealing under inert gas atmosphere at the claimed temperatures. Ates is directed to annealing effects on optical and electrical properties of indium selenide films, and teaches annealing such films under an inert gas atmosphere at temperatures within the claimed range (see Abstract; Experimental Section at Pg. 2). According to Ates, annealing temperature is result-effective with regard to film resistance values (Id.). Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have conducted annealing under an inert atmosphere as claimed in the method of Ashok in order to obtain a desired film resistance value. Additionally, Ashok is noted as citing Ates (see Ashok Reference 9 at Pg. 6). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael P Rodriguez whose telephone number is (571)270-3736. The examiner can normally be reached 9:00 - 6:00 Eastern M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at 571-272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael P. Rodriguez/Primary Examiner, Art Unit 1712
Read full office action

Prosecution Timeline

Sep 27, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+29.1%)
2y 8m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 683 resolved cases by this examiner. Grant probability derived from career allowance rate.

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