DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claims 1, 11 and 17, the recitation of “a first interface box sharing the transfer module and configured to transfer the wafer to the scanner and to match vacuum degrees of the transfer module and the scanner” (for example, see claim 1) is ambiguous. The term “vacuum degrees” and the recited limitation of “matching vacuum degrees” render the scope of the claims indefinite because the claims fall to specify the parameter by which vacuum is measured, the reference level to which matching occurs, and the degree of matching required. One of ordinary skill in the art would not be reasonably apprised of the metes and bounds of the claimed invention.
As to claim 16, the limitation of “ a second interface box configured to move the wafer to and from the transfer module between at least one of the plurality of process modules and the transfer module” renders the scope of the claim unclear because: it is ambiguous whether the second interface box is positioned between the transfer module and a single process module, multiple process modules, or is movable relative thereto. Furthermore, it is unclear whether the interface box forms part of the transfer module or is a separate load-lock structure.
Also, claim 16 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. The omitted element is a first interface box.
For purposes of examination, the claims are interpreted under the broadest reasonable interpretation consistent with the specification. For example, the term “interface box” is interpreted as any chamber or module disposed between wafer handling environments and configured to facilitate wafer transfer and/or environmental transition, including but not limited to load-lock chambers, buffer modules, or transfer interface modules. The phrase “between at least one of the plurality of process modules and the transfer modules” is interpreted as encompassing an interface structure positioned between the transfer module and one or more process modules. The ordinal term “second interface box” is interpreted as denoting an additional interface structure and does not require the presence of a first interface box unless explicitly recited. Finally, the limitation “match vacuum degrees” is interpreted broadly as establishing compatible pressure environments sufficient to permit wafer transfer between modules without compromising process conditions.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 10 and 11-12, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Auer-Jongepier et al (U.S.Pat. 7,145,643).
With respect to claim 1, Auer- Jongepier discloses a lithography track system (abstract; figure 1) comprising all features of the instant claim such as: a plurality of process modules (41-45) each configured to perform a photolithography process on a wafer (W); a transfer module (20) configured to transfer the wafer between the plurality of process modules; a scanner (1; 26) at one end of the transfer module and configured to expose a photoresist material on the wafer and a first transfer interface box (10) sharing the transfer module and configured to transfer the wafer to the scanner and to match vacuum degrees of the transfer module and the scanner (see col.14, lines 45-48 which indicates environmental conditioning between interface and scanner ).
As to claims 2 and 11, Auer-Jongepier discloses the plurality of process modules have: a coating process module configured to coat the wafer with photoresist; a baking process module (43; FEB) configured to bake the coated or exposed wafer (W) and a dry development module (44) configured to dry-remove the exposed wafer or a pattern thereon.
As to claim 3, wherein the first interface box has at least one of a baking process module, an alignment module, a buffer module (41) and a cleaning module (42).
As to claim 10, wherein an arrangement of the process module and the transfer module is a track-type (see figures 2-3).
As to claim 12, wherein the first interface box (10) is formed continuously with the transfer module (20) and has at least one of a baking process module, an alignment module, a buffer module and a cleaning module (see col. 11, lines 40-46).
With respect to claims 5 and 16, Auer-Jongepier discloses a lithographic track system (see figure 5) comprising: an equipment front-end module (LL) configured to supply a wafer (W); a plurality of process modules (41-44) configured to sequentially or simultaneously process the wafer; a transfer module (20) having a first end connected to the equipment front-end module and configured to transfer the wafer and a second interface box (10) configured to move the wafer to and from the transfer module between at least one of the plurality of process modules and transfer module.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Auer-Jongepier et al (U.S.Pat. 7,145,643) in view of Hughes et al (U.S.Pat. 4,241,165).
With respect to claim 4, Auer-Jongepier discloses a lithography track system comprising substantially all features of the instant as discussed above. Auer-Jongepier does not expressly disclose a plasma device within the first interface box. This feature, however, is well known in the art. For example, Hughes disclose a lithography track system and discloses plasma processing devices used for photoresist treatment, including plasma development and resist removal processes (see col.2, lines 15-25). It would have been obvious to provide a plasma device as taught by Hughes within the interface unit of the lithography track system of Auer-Jongepier in order to perform removal or surface conditioning prior to substrate transfer, as plasma processing was well known in semiconductor substrate fabrication.
Claims 6-8, 14-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Auer-Jongepier et al (U.S.Pat. 7,145,643) in view of Vellore et al (US 2008/0224817 A1).
With respect to claims 6-8, 14-15 and 17, Auer-Jongepier discloses a lithography track system comprising substantially all limitations of the claims as discussed, except for a second interface box having a wafer-in chamber; a wafer-out chamber and a robot arm between the wafer-in-chamber and the wafer-out-chamber, as recited. Vellore discloses a lithography track system (see figure 1) having a second interface box (110-114) having a wafer-in-chamber (112), a wafer-out-chamber (114) and a robot arm (118; 124, 128) for transfer the wafer from the wafer-in-chamber to the process chamber and from the process module to the wafer- out-chamber. It would have been obvious to a skilled artisan before the effective filling date of the claimed invention to employ the second interface box as taught by Vellore into the lithography track system of Auer-Jongepier to improve the quality of the lithography system.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Auer-Jongepier et al (U.S.Pat. 7,145,643).
As to claims 18-20, Auer-Jongepier discloses a lithography track system comprising substantially all of the limitations of the instant claims as demonstrated above. Auer-Jongepier does not expressly disclose the scanner being connected to a second end of the transfer module as recited in the instant claims. It would have been obvious to a skilled artisan before the effective filling date of the claimed invention to connect the scanner to a second end of the transfer module and place the first interface box in line with the transfer module adjacent the scanner, as recited in the claims for the purpose of improving the quality of the lithography track system since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Yu et al (U.S.Pat. 12,278,125); Babbs et al (U.S.Pat. 11,658,051) disclose lithography track systems and have been cited for technical background.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG HENRY NGUYEN whose telephone number is (571)272-2124. The examiner can normally be reached Monday-Friday 7:00AM-4:30PM.
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HUNG HENRY NGUYEN
Primary Examiner
Art Unit 2882
Hvn
2/10/26
/HUNG V NGUYEN/ Primary Examiner, Art Unit 2882