DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/27/2024 is being considered by the examiner.
Drawings
The drawings submitted on 09/27/2024 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over Hayashi et al. (US 20210134762 A1) in view of Nakashima et al. (US 20200185359 A1).
Regarding claim 1, Hayashi discloses a semiconductor module comprising:
at least one substrate (11A) including a first electrode pattern (211A), a second electrode pattern (212), and a third electrode pattern (214A), the first electrode pattern (211A) being positioned between the second electrode pattern (212) and the third electrode pattern (2A)1 in plan view; (Fig. 3 and 8) and
a plurality of semiconductor switching elements (31) that each have a first surface (bottom) to be joined to the first electrode pattern (211A), and a second surface (top) facing in an opposite direction to the first surface, wherein:
on the second surface (top), a control electrode (313), a control line (421) to be connected to the control electrode (313), and a main electrode (311) including a plurality of regions (311A/311B) are provided,
each of the regions (311A/311B) is electrically connected to the second electrode pattern (212) via a first wire (41), and is electrically connected to the third electrode pattern via (214A) a second wire (431), ([0080], Fig. 15)
the second electrode pattern (212) is a pattern for a principal current (from terminal 24),
Hayashi does not disclose:
a plurality of regions divided by the control line are provided, and
the third electrode pattern is used as an auxiliary pattern for control.
However, Nakashima discloses:
a plurality of regions (17) divided by the control line (15) are provided, and
the third electrode pattern (11) is used as an auxiliary pattern for control (per [0096]).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hayashi and Nakashima to arrive at the claimed invention so that “the gate oscillation is reduced or suppressed without increasing power loss in the plurality of semiconductor switching elements” (Nakashima, [0018])
Regarding claim 2, Hayashi discloses the semiconductor module according to claim 1, further comprising a first control terminal (281A) to be joined to the third electrode pattern (214A). ([0118], Fig. 8)
Regarding claim 3, Hayashi discloses the semiconductor module according to claim 2, wherein:
the third electrode pattern (214A) has an elongated shape, ([0079], Fig. 8) and
a distance between (i) a joining place between the third electrode pattern and the first control terminal (281A), and (ii) a center of the third electrode pattern (214A) in a length direction thereof is less than a distance between (i) the joining place between the third electrode pattern and the first control terminal, and (ii) each of ends of the third electrode pattern (214A) in the length direction. (Fig. 3)
Regarding claim 4, Hayashi discloses the semiconductor module according to claim 2, further comprising a second control terminal (27A), wherein:
the at least one substrate (11) further includes a fourth electrode pattern (213A) to be electrically connected to the control electrode (313) via a third wire (421), ([0076], Fig. 15)
the second control terminal (27A) is joined to the fourth electrode pattern (213A), and
the third electrode pattern (214A) is positioned between the first electrode pattern (211A) and the fourth electrode pattern (213A) in plan view. (Fig. 8)
Regarding claim 5, Hayashi discloses the semiconductor module according to claim 2, further comprising a second control terminal (27A), wherein:
the at least one substrate (11) further includes a fourth electrode pattern (213A) to be electrically connected to the control electrode (313) via a third wire (421), ([0076], Fig. 15)
the second control terminal (27A) is joined to the fourth electrode pattern (213A), and
Hayashi does not disclose:
the fourth electrode pattern is positioned between the first electrode pattern and the third electrode pattern in plan view.
However, Nakashima discloses:
the fourth electrode pattern (10) is positioned between the first electrode pattern (8) and the third electrode pattern (11) in plan view. (Fig. 14)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hayashi and Nakashima to have the fourth electrode pattern is positioned between the first electrode pattern and the third electrode pattern in plan view, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 so that “the gate oscillation is reduced or suppressed without increasing power loss in the plurality of semiconductor switching elements” (Nakashima, [0018])
Regarding claim 6, Hayashi discloses the semiconductor module according to claim 2, wherein:
the at least one substrate (11) comprises a plurality of substrates (11A/11B/11C) each having the first electrode pattern (211/221/231), the second electrode pattern (212/222/232), and the third electrode pattern (214/224/234), and
the first control terminal (281A) is joined (by 263) to the third electrode pattern (214/224/234) of each of the substrates (11A/11B/11C). (Fig. 10)
Regarding claim 7, Hayashi discloses the semiconductor module according to claim 6, further comprising a fourth wire (263) that is electrically connected to the third electrode pattern (214/224/234) of each of the plurality of substrates (11A/11B/11C). (Fig. 10)
Regarding claim 8, Hayashi discloses the semiconductor module according to claim 1, wherein the semiconductor switching elements (31) are electrically connected in parallel (per [0129])
Regarding claim 9, Hayashi discloses the semiconductor module according to claim 1. Hayashi does not disclose wherein the second wire for each of the regions comprises a plurality of wires.
However, Nakashima discloses:
the second wire (16) for each of the regions (17) comprises a plurality of wires (per Fig. 23).
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hayashi and Nakashima for similar reasons mentioned beforehand.
Regarding claim 10, Nakashima discloses the semiconductor module according to claim 1, further comprising a plurality of semiconductor elements (12) that each have:
a third surface (bottom) to be joined to the first electrode pattern (8); and
a fourth surface (top) facing in an opposite direction to the third surface, wherein
an intermediate portion of the second wire (16) is joined to the fourth surface (top). (Fig. 9)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Hayashi and Nakashima for similar reasons mentioned beforehand.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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