DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 12/1/2025. Claims 1-8 and 10-21 are pending and have been examined. Claim 9 has been cancelled. Claims 1, 8, 13 and 17-20 have been amended. Claim 21 has been added.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 and 10-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cohen et al. (US 20220100519 A1) and in further in view of Venkatachar et al. (US 20220075624 A1).
In regards to claim 1, Cohen discloses a device (Figure 1 and [0014] “processor 100 is part of one of a variety of electronic devices”) comprising: a plurality of fetch pipelines each configured to fetch instructions (Figure 1 and [0016] “the processor 100 includes a plurality of fetch and decode pipelines, including fetch and decode pipelines 112 and 113. It will be appreciated that in some embodiments the processor 100 includes additional fetch and decode pipelines not illustrated at FIG. 1. Each fetch and decode pipeline is configured to fetch instructions from an instruction cache 110”) wherein at least two of the plurality of fetch pipelines share a common cache (Figure 1 and [0016] "Each fetch and decode pipeline is configured to fetch instructions from an instruction cache 110 and to decode each fetched instruction into one or more operations) a control circuit configured to assign groups of instructions to the plurality of fetch pipelines independent from program order (Figure 1 and [0021] “the control module 106 selects one of the fetch and decode pipelines 112 and 113 and provides the corresponding fetch stream to the selected fetch and decode pipeline, which fetches the sequence of instruction bytes of the branch window” and [0035] “the control module 106 assigns fetch streams to the fetch and decode pipelines 112 and 113 such that instructions are processed out of order relative to an overall program flow associated with the instruction stream 101”; and additionally, “control circuitry of the reorder control module 138” is interpreted as being part of the control circuit); and a dispatch circuit configured to receive groups of decoded operations, corresponding to the assigned groups of instructions, from the plurality of fetch pipelines via a multiplexer, coupled to each of the plurality of fetch pipelines, in program order (Figure 1 & 5 and [0035] “the processor 100 includes a reorder control module 538 placed between the fetch and decode pipelines 112 and 113 and a dispatch unit 539” and [0036] “The reorder control module 138 provides the reordered operations to the dispatch unit 539” which [0039] “restore the received operations to the sequence indicated by a program flow of the instruction stream 101”; in other words, the selection aspect of the reorder control module is interpreted as a multiplexer since it has to select among multiple fetch pipeline outputs to feed into the dispatch unit and the [0037] "reorder control module 138 includes a separate FIFO buffer for each of the fetch and decode pipelines 112 and 113").
Cohen does not disclose wherein at least two of the plurality of fetch pipelines share a common operation cache. While Cohen discloses fetch pipelines sharing a common instruction cache, Cohen does not disclose an operation cache and thus does not disclose sharing of an operation cache.
Venkatachar discloses a pipeline using an operation cache (Venkatachar Figure 3 and [0032] “The portion 300 also includes an operation cache (OC) 355 that caches previously decoded instructions, which are held in the operation cache 355 until they are provided to the multiplexer 345)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cohen by incorporating the common function of the instruction cache of Cohen with the operation cache of Venkatachar to result in a common operation cache. Doing so would reduce hardware redundancy and improve resource utilization by allowing multiple fetch pipelines to access a shared pool of predecoded operations.
In regards to claim 2, the combination of Cohen and Venkatachar discloses the device of claim 1 (see rejection of claim 1 above) wherein the control circuit is further configured to provide a control signal to the multiplexer for selecting between the plurality of fetch pipelines to output to the dispatch circuit (Cohen: The control circuitry of the reorder control module is interpreted as being part of control circuit as described in claim 1, which employs [0037] “control information to restore the order of the operations stored at the separate FIFO buffers”; in other words, FIFO buffers corresponding to fetch pipelines are selected by a control signal based on control information from the control circuitry of the reorder control module, i.e. multiplexer)
In regards to claim 3, the combination of Cohen and Venkatachar discloses the device of claim 2 (see rejection of claim 2 above) wherein the control signal is triggered based on outputting a last operation of at least one of the groups of decoded operations to the dispatch circuit (Cohen [0037] teaches that control information includes "the FIFO end entry address (that is, the address of the FIFO buffer entry that stores the operation corresponding to the last instruction of a fetch window)"; in other words, using control information, when the last instruction is reached, a signal would trigger switching to a FIFO buffer having the next operation in program order).
In regards to claim 4, the combination of Cohen and Venkatachar discloses the device of claim 3 (see rejection of claim 3 above) wherein the last operation includes a pointer to a next fetch pipeline of the plurality of fetch pipelines, the next fetch pipeline includes a next decoded operation after the last operation in the program order, and the control signal corresponds to a selection signal for the multiplexer to switch to the next fetch pipeline (Cohen [0026] "next instruction address is indicated by the last instruction of the initial branch window. The next instruction address denotes the start of another fetch stream to be fetched and decoded" and this information is included in the control information [0037] "the FIFO end entry address (that is, the address of the FIFO buffer entry that stores the operation corresponding to the last instruction of a fetch window)" along with instruction/block sequence numbers for each operation, the FIFO buffer that stores the block start operation, and the FIFO start entry address, etc. In other words, control information is used to switch to the next fetch pipeline, i.e. corresponding FIFO buffer, and after reaching the last operation, it points to such next fetch pipeline. Therefore, [0037] “Control circuitry of the reorder control module 138 employs this control information to restore the order of the operations stored at the separate FIFO buffers”).
In regards to claim 5, the combination of Cohen and Venkatachar discloses the device of claim 4 (see rejection of claim 4 above) wherein the control signal corresponds to toggling between two of the plurality of fetch pipelines when the last operation is encountered (Cohen: Figure 1 shows an example embodiment with two fetch-decode pipelines [0016] “including fetch and decode pipelines 112 and 113”; in other words, when the last operation is encountered, the pipelines will switch between each other which is interpreted as toggling).
In regards to claim 6, the combination of Cohen and Venkatachar discloses the device of claim 4 (see rejection of claim 4 above) wherein the control signal corresponds to selecting the pointer to the next fetch pipeline based on a round-robin scheme (Cohen: Figure 1 shows an example embodiment with two fetch-decode pipelines [0016] “including fetch and decode pipelines 112 and 113”; in other words, for two fetch pipelines, switching between each other is interpreted as toggling and is therefore a two-resource version of the circular distribution pattern defined by round-robin).
In regards to claim 7, the combination of Cohen and Venkatachar discloses the device of claim 4 (see rejection of claim 4 above) wherein the last operation corresponds to a last operation of a first thread before switching to a second thread (Cohen [0030] “In some embodiments, the fetch streams to be processed by the fetch and decode pipelines 112 and 113 are associated with different program threads executing at the processor 100. That is, the instruction bytes for one fetch stream are instruction bytes of one thread while the instruction bytes of another fetch streams are instruction bytes of another thread. In these embodiments, the control module 106 assigns fetch streams to the fetch and decode pipelines 112 and 113 based in part on the thread associated with each fetch stream”; in other words, when the last operation of a first thread is dispatched, it switches to a FIFO queue corresponding to the fetch pipeline of a second thread).
In regards to claim 8, the combination of Cohen and Venkatachar thus far discloses the device of claim 1 (see rejection of claim 1 above) wherein at least one of the plurality of fetch pipelines includes: a fetch queue configured to store at least one of the assigned groups of instructions (Cohen [0011] "each fetch and decode pipeline of the processor includes an input queue to store instructions to be processed" as shown by input queues 225 and 226 of figure 2); the common operation cache configured to store predecoded operations (Venkatachar: Figure 3 and [0032] “The portion 300 also includes an operation cache (OC) 355 that caches previously decoded instructions, which are held in the operation cache 355 until they are provided to the multiplexer 345” (note: Cohen Figure 1 and [0016] disclose "Each fetch and decode pipeline is configured to fetch instructions from an instruction cache 110 and to decode each fetched instruction into one or more operations" and the combination of references disclose the above limitation regarding a common operation cache)) and an instruction cache configured to store instructions to be decoded by the decode circuit (Cohen: Figure 1 and [0016] "Each fetch and decode pipeline is configured to fetch instructions from an instruction cache 110 and to decode each fetched instruction into one or more operations").
The combination of Cohen and Venkatachar thus far does not disclose an operation cache fetch queue configured to store instructions to be fetched from the operation cache; a decode circuit configured to decode instructions not found in the operation cache.
Venkatachar discloses an operation cache fetch queue configured to store instructions to be fetched from the operation cache (Instructions are conveyed to buffer 320 where corresponding operations are [0032] “held in the operation cache 355 until they are provided to the multiplexer 345” as shown in figure 3); a decode circuit configured to decode instructions not found in the operation cache (Figure 3 and [0030] “Instructions that are ready for decoding are pushed out of the instruction cache 330 to a decoder 340 (via the buffer 335) and the decoder 340 performs decoding of the instructions” and [0032] “The portion 300 also includes an operation cache (OC) 355 that caches previously decoded instructions, which are held in the operation cache 355 until they are provided to the multiplexer 345”; in other words, instructions are directed to be decoded if not found in operation cache 355).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cohen by incorporating the teachings of Venkatachar to include an operation cache fetch queue configured to store instructions to be fetched from the operation cache; and that the decode circuit of Cohen is modified and configured to decode instructions not found in the operation cache. Doing so would predictably improve the efficiency of Cohen’s instruction fetching and decoding pipeline process by avoiding redundant decoding of instructions that are frequently executed.
In regards to claim 10, the combination of Cohen and Venkatachar discloses the device of claim 8 (see rejection of claim 8 above) wherein at least two of the plurality of fetch pipelines share a common instruction cache (Cohen [0016] "Each fetch and decode pipeline is configured to fetch instructions from an instruction cache 110 and to decode each fetched instruction into one or more operations").
In regards to claim 11, the combination of Cohen and Venkatachar discloses the device of claim 1 (see rejection of claim 1 above) wherein at least one of the plurality of fetch pipelines includes an operation queue configured to store decoded operations from the respective fetch pipeline (Cohen [0037] "reorder control module 138 includes a separate FIFO buffer for each of the fetch and decode pipelines 112 and 113"; in other words the FIFO buffers are interpreted as operation queues for their corresponding fetch pipelines), and the multiplexer is coupled between the operation queue and the dispatch circuit (Cohen: From claim 1, the control circuitry of the reorder control module that performs the switching based on control information is interpreted as the multiplexer. Therefore, the multiplexer is coupled between operation queues, including the operation queue, i.e. a fetch pipeline’s corresponding FIFO buffer, and the dispatch circuit 539 as shown in Figure 5).
In regards to claim 12, the combination of Cohen and Venkatachar discloses the device of claim 1 (see rejection of claim 1 above) wherein the control circuit is further configured to assign the groups of instructions to the plurality of fetch pipelines based on a branch predictor circuit (Cohen [0019] "to determine the initial and end instruction for each fetch stream, the processor 100 employs branch windows 104 identified by a branch predictor 102").
Regarding claim 13, the claim recites a system which is similar to the device of claims 1, 2, and 8, and is therefore rejected on the same premises.
Cohen further teaches a memory and a processor ([0023] “memory or other storage component (not shown) of the processor 100”).
Regarding claims 14, 15, 16, and 18, the claims recite a system which is similar to the device of claims 3, 4, 7, and 12 respectively, and is therefore rejected on the same premises.
Regarding claim 17, the claim recites a system which is similar to the device of claim 10, and is therefore rejected on the same premises.
Regarding claim 19, the claim recites a method which is similar to the device of claims 1, 8, and 11, and is therefore rejected on the same premises.
Regarding claim 20, the claim recites a method which is similar to the device of claim 3, and is therefore rejected on the same premises.
Claim(s) 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cohen, Venkatachar and in further in view of Cohen (PGPUB No. 2022/0100663, cited on 892 filed on 9/23/2025) hereby referred to as Cohen 663’.
In regards to claim 21, the combination of Cohen and Venkatachar discloses The device of claim 8 (see rejection of claim 8 above) wherein the common operation cache (Venkatachar: Figure 3 and [0032] “The portion 300 also includes an operation cache (OC) 355 that caches previously decoded instructions, which are held in the operation cache 355 until they are provided to the multiplexer 345” (note: Cohen Figure 1 and [0016] disclose "Each fetch and decode pipeline is configured to fetch instructions from an instruction cache 110 and to decode each fetched instruction into one or more operations" and the combination of references disclose the above limitation regarding a common operation cache))
The combination of Cohen and Venkatachar does not disclose the common operation cache includes input ports reserved for each of the at least two of the plurality of fetch pipelines.
Cohen 663’ discloses an operation cache includes input ports reserved for each of at least two of the plurality of pipelines. ([0026 and 0039]: wherein an operation cache includes read ports designated for at least two pipelines)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the common operation cache of Cohen and Venkatachar, shared between pipelines, to include designated read ports for multiple pipelines as the operation cache of Cohen 663’. It would have been obvious to one of ordinary skill in the art because designated read ports can allow pipelines to independently read instruction bytes as to enable the pipelines to operate concurrently (e.g. increasing instruction throughput) (Cohen 663’ [0026]).
Response to Arguments
Applicant’s arguments, see page 9 of the remarks, filed on 12/1/2025, with respect to previous claim objections, specification objections and 35 USC 112(b) rejections have been fully considered and are persuasive. Thus, the previous claim objections, specification objections and 35 USC 112(b) rejections have been withdrawn.
Applicant's arguments filed on 12/1/2025, regarding 35 USC 103 rejections in view of Cohen and Venkatachar of independent claims 1, 13 and 19 have been fully considered but they are not persuasive. Thus, the previous 35 USC 103 rejections of claims 13 and 19 are maintained. The previous 35 USC 102 rejection of claim 1 has been withdrawn, and now is rejected under 35 USC 103 in view of Cohen and Venkatachar.
Claims 2-8, 10-12, 14-18 and 20-21 are argued at least based upon their dependencies on one of the independent claims above and therefore remain rejected at least based upon their dependencies.
Applicant argues the 35 USC 103 rejections in view of Cohen and Venkatachar, on pages 10-11 of the remarks, in the substance that:
“With respect to original claim 9, the Office Action relies on Venkatachar as allegedly disclosing "wherein at least two of the plurality of fetch pipelines share a common operation cache." However, the Office Action does not state the Venkatachar suggests these features, but argues that "the common function of the instruction cache of Cohen with the operation cache of Venkatachar to result in a common operation cache." See page 12 of the Office Action. However, as the instruction cache of Cohen and the operation cache of Venkatachar are different structures having different functions and different positions within respective pipelines, the alleged modification would not be obvious.
Cohen thus does not disclose "at least two of the plurality of fetch pipelines share the common operation cache," as recited by claim 13. The Office Action does not allege that Venkatachar discloses this language of claim 13. As such, even if one of ordinary skill would have been led to modify Cohen based on Venkatachar in the manner proposed by the Office Action (which Applicant does not concede), the Office Action's proposed modification would not have disclosed at least the quoted language of claim 13.
For at least these reasons, claim 13 patentably distinguishes any combination of Cohen and Venkatachar. Withdrawal of the rejections under §§ 102 and 103 of claims 1 and of each claim that depends therefrom is respectfully requested.
For reasons that should be appreciated from the foregoing, Cohen does not disclose: - "at least two of the plurality of fetch pipelines share the common operation cache," recited in claim 1; or - "fetching, for the assigned group of instructions, predecoded operations available in a common operation cache in the selected fetch pipeline, wherein at least two of the plurality of fetch pipelines share the common operation cache," recited in claim 19.
For at least these reasons, claims 1 and 19 patentably distinguish Cohen and Venkatachar. Withdrawal of the rejections of claims 1 and 19 and of each claim that depends therefrom under § 103 is respectfully requested.”
It appears the applicant is arguing that the combination of Cohen and Venkatachar would not disclose “at least two of the plurality of fetch pipelines share a common operation cache” because each reference discloses two different cache structures having different functions and different positions within respective pipelines and thus the combination would not be obvious. The examiner respectfully disagrees.
The examiner first clarifies that the previous rejection was indicating that the combination of Cohen and Venkatachar would disclose the limitation because Cohen discloses “at least two fetch pipelines share a common instruction cache” (See Cohen Fig. 1 and [0016]), however Cohen does not disclose an operation cache. However, Venkatachar discloses an operation cache which is a shared common resource of a pipeline (see [0032] “the operation cache 355 is a common resource that is shared by the main path and the alternate path, e.g., to support time multiplexing of the resources of the pipeline”). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the device of Cohen, which discloses a plurality of fetch pipelines that share a common cache, to share a common operation cache as taught in Venkatachar. It would have been obvious because it would have been applying a known technique (using a shared common operation cache in a pipeline to store pre-decoded operations as taught in Venkatachar) to a known device (device of Cohen which includes two fetch pipelines which share a common cache) ready for improvement to yield predictable results (allowing two fetch pipelines to share a common operation cache which stores pre-decoded operations) for the benefit of improving the efficiency of Cohen’s instruction fetching and decoding pipelines process by avoiding redundant decoding of instructions that are frequently executed (See MPEP 2143, Example D).
Furthermore, although both caches have different functions and different locations relative to the respective pipelines both structures are still well-known cache data structures used in computer architecture. And allowing Cohen to include a shared common operation cache as taught in Venkatachar would not change the functionality of the operation cache, but rather improve the fetch and decode pipelines of Cohen by allowing them to bypass decoding for frequently executed instructions which would provide various benefits known in the art from including an operation cache in a pipeline such as decreased latency from bypassing a decoder block, improved energy efficiency from reduced power consumption, increased fetch bandwidth, etc. (Said another way the combination is modifying two pipelines which share a common cache to share an additional well-known cache (operation cache) which is also a commonly shared resource (Venkatachar [0032]). And it is well-known in computer architecture art the benefits and advantages of including an operation cache in a pipeline and those benefits make the combination of Cohen and Venkatachar obvious.)
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
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